Patents by Inventor Robert W. Martell

Robert W. Martell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170109575
    Abstract: In one embodiment, a safety label management system includes a mobile device comprising a camera, a label database, a safety label printer configured to print safety labels, and a computing unit in electronic communication with the mobile device, the label database, and the safety label printer. The mobile device may be configured to capture, via the camera, an image of an existing safety label. The label database may store a plurality of database entries, each entry including a unique label ID number, a set of label characteristics, and a printable label file. The computing unit may be configured to: process the image to identity label characteristics of the existing safety label; compare the label characteristics of the existing safety label to the label characteristics of the label database entries; and prompt a user to perform an action.
    Type: Application
    Filed: October 14, 2016
    Publication date: April 20, 2017
    Inventors: Robert W. Martell, Kevin M. Parks
  • Publication number: 20170017863
    Abstract: Printing systems including a printing mechanism for printing adjacent print passes and a computing system are shown and described. Memory of the computing system includes computer-readable instructions for: receiving calibration data; receiving graphical data having first and second sets of perimeter graphical data; generating a first set of longitudinal boundary graphical data based on the first set of perimeter graphical data and the calibration data; generating a second set of longitudinal boundary graphical data based on the second set of perimeter graphical data and the calibration data; printing a first print pass having a first perimeter print area and a first longitudinal boundary area; printing a second print pass having a second perimeter print and a second longitudinal boundary area; and blending the first and the second longitudinal boundary areas to generate an at least partially overlapping longitudinal boundary area.
    Type: Application
    Filed: July 14, 2015
    Publication date: January 19, 2017
    Inventors: Robert W. Martell, Kevin M. Parks
  • Patent number: 9463577
    Abstract: Paper cutting mechanisms for cutting paper in a printing device including a drive mechanism, a cutting device coupled to the drive mechanism, and a retention mechanism including a trigger and a retaining portion configured to mechanically interact with the cutting device to selectively deploy the retention mechanism to retain the paper. In some examples, paper cutting mechanism includes a trigger including an elbow, a first arm extending from the elbow, and a second arm extending from the elbow offset from the first arm, and a rotation shaft extending from the elbow transverse to a plane defined by the first arm and the second arm. In some further examples, the paper cutting mechanism includes a resilient member cooperatively coupled with a paper engaging end of the retaining portion.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: October 11, 2016
    Inventors: Tim Martin, Robert W. Martell, Dan Meyer
  • Publication number: 20160288484
    Abstract: End caps for printing substrate rolls that are configured to engage with a print roll retaining mechanism of a printer in order to regulate total web tension of a printing substrate during a printing operation are shown and described. Each of the end caps has a cylindrical body including an attachment mechanism for attaching the end cap to the printing substrate roll; a continuously curved outer wall longitudinally aligned with the cylindrical body and configured to define a first component of the total web tension; and a central protuberance that is concentric with the continuously curved outer wall and longitudinally aligned with the cylindrical body, an outer face of the central protuberance being extended beyond an outer lip edge of the curved outer wall, the central protuberance configured to define a second component of the total web tension.
    Type: Application
    Filed: March 31, 2015
    Publication date: October 6, 2016
    Inventors: Kasey Coussens, Daniel B. Meyer, Robert W. Martell
  • Patent number: 9193196
    Abstract: Printer head shuttles configured to control contact pressure of one or more printer head assemblies against a printing substrate and an underlying platen during a printer operation are shown and described. The printer head shuttles include a shuttle guide and a shuttle main body having one or more printer head assemblies. Each printer head assembly includes an axel attached to the shuttle main body, an assembly main body pivotably attached to the axel, a mounting plate attached to the assembly main body, a printer head attached to the mounting plate, and a drive mechanism for pivoting the head assembly between a substrate compressing position and a substrate non-compressing position.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: November 24, 2015
    Inventors: Daniel B. Meyer, Robert W. Martell, Stacy Foos, Jian-Hua Chen, Tsan-Fang Yu, Feng-Yi Tai
  • Publication number: 20150273716
    Abstract: Paper cutting mechanisms for cutting paper in a printing device including a drive mechanism, a cutting device coupled to the drive mechanism, and a retention mechanism including a trigger and a retaining portion configured to mechanically interact with the cutting device to selectively deploy the retention mechanism to retain the paper. In some examples, paper cutting mechanism includes a trigger including an elbow, a first arm extending from the elbow, and a second arm extending from the elbow offset from the first arm, and a rotation shaft extending from the elbow transverse to a plane defined by the first arm and the second arm. In some further examples, the paper cutting mechanism includes a resilient member cooperatively coupled with a paper engaging end of the retaining portion.
    Type: Application
    Filed: April 1, 2014
    Publication date: October 1, 2015
    Inventors: Tim Martin, Robert W. Martell, Dan Meyer
  • Patent number: 8553055
    Abstract: A thermal printer is operated to adjust the level of energy applied to print elements of a print head of the printer in response to selected changes in signals corresponding to the voltage from a power source used to provide energy to the printing elements. Voltage changes that occur during printing of a print can be ignored. In addition, voltage changes occurring when a printer is not being powered by a battery can also be ignored. Rapid decreases in voltage of the power source can be detected and accounted for. In addition, increasing voltages of the power source can also be determined and accounted for.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: October 8, 2013
    Assignee: Graphic Products, Inc.
    Inventors: Robert W. Martell, Mark E. Thueson
  • Patent number: 8482586
    Abstract: An entire block of print data for a message is subdivided into sub-blocks of print data. During printing of sub-blocks, an earlier received sub-block of data is used to print one portion of a substrate moving in the downstream direction. The substrate is moved upstream for a back distance and then moved downstream with the next sub-block of data being printed on the substrate as it is moved downstream. As a back distance section of the substrate again travels in the downstream direction, data from the subsequent sub-block of data that corresponds to data printed on the back distance section of the substrate during printing of the immediately preceding sub-block of data, is printed on the back distance section of the substrate. The sub-blocks of data are in effect stitched together by the dual printed back distance to minimize transition artifacts.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: July 9, 2013
    Assignee: Graphic Products, Inc.
    Inventors: Robert W. Martell, Paul D. Scott, Giancarlo R. Villanueva, Kevin M. Parks
  • Patent number: 8477162
    Abstract: A thermal printer, when operating under battery power, has an internal or battery ground. Static electricity is typically generated during normal operation of the printer. At least one static electricity discharge member is positioned in contact with a major surface of printing substrate at a location downstream from the location at which a thermal print head transfers ink from an ink transfer ribbon to the substrate. The at least one static electricity discharge member is electrically coupled to the internal ground so as to discharge static electricity build up that can otherwise damage electronic components of the printer.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: July 2, 2013
    Assignee: Graphic Products, Inc.
    Inventors: Robert W. Martell, Mark E. Thueson, Kevin M. Parks, Divyatej Tummala, Daniel B. Meyer, Timothy C. Martin
  • Patent number: 7208402
    Abstract: An apparatus comprising: a die having a top metal layer, the top metal layer comprised of at least a first metal line and a second metal line; a passivation layer covering the top metal layer; a C4 bump on the passivation layer; and a first passivation opening and a second passivation opening in the passivation layer, the first passivation opening to connect the first metal line to the C4 bump, and the second passivation opening to connect the second metal line to the C4 bump.
    Type: Grant
    Filed: June 3, 2005
    Date of Patent: April 24, 2007
    Assignee: Intel Corporation
    Inventors: Mark T. Bohr, Robert W. Martell
  • Patent number: 7180195
    Abstract: An apparatus comprising: a die having a top metal layer, the top metal layer comprised of at least a first metal line and a second metal line; a passivation layer covering the top metal layer; a C4 bump on the passivation layer; and a first passivation opening and a second passivation opening in the passivation layer, the first passivation opening to connect the first metal line to the C4 bump, and the second passivation opening to connect the second metal line to the C4 bump.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: February 20, 2007
    Assignee: Intel Corporation
    Inventors: Mark T. Bohr, Robert W. Martell
  • Patent number: 6393550
    Abstract: Maximum throughput or “back-to-back” scheduling of dependent instructions in a pipelined processor is achieved by maximizing the efficiency in which the processor determines the availability of the source operands of a dependent instruction and provides those operands to an execution unit executing the dependent instruction. These two operations are implemented through a number of mechanisms. One mechanism for determining the availability of source operands, and hence the readiness of a dependent instruction for dispatch to an available execution unit, relies on the early setting of a source valid bit during allocation when a source operand is a retired or immediate value. This allows the ready logic of a reservation station to begin scheduling the instruction for dispatch.
    Type: Grant
    Filed: September 19, 1995
    Date of Patent: May 21, 2002
    Assignee: Intel Corporation
    Inventors: Michael A. Fetterman, Glenn J. Hinton, Robert W. Martell, David B. Papworth
  • Patent number: 6101597
    Abstract: Maximum throughput or "back-to-back" scheduling of dependent instructions in a pipelined processor is achieved by maximizing the efficiency in which the processor determines the availability of the source operands of a dependent instruction and provides those operands to an execution unit executing the dependent instruction. These two operations are implemented through number of mechanisms. One mechanism for determining the availability of source operands, and hence the readiness of a dependent instruction for dispatch to an available execution unit, relies on the prospective determination of the availability of a source operand before the operand itself is actually computed as a result of the execution of another instruction. Storage addresses of the source operands of an instruction are stored in a content addressable memory (CAM).
    Type: Grant
    Filed: December 30, 1993
    Date of Patent: August 8, 2000
    Assignee: Intel Corporation
    Inventors: Robert P. Colwell, Michael A. Fetterman, Glenn J. Hinton, Robert W. Martell, David B. Papworth
  • Patent number: 5842036
    Abstract: An out-of-order execution processor comprising an execution unit, a storage unit and a scheduler is disclosed. The storage unit stores instructions awaiting availability of resources required for execution. The scheduler periodically determines whether resources required for executing each instruction are available, and if so, dispatches that instruction to the execution unit. The execution unit indicates future availability of hardware resources such as functional units and write back ports a number of clock cycles before actual availability of the hardware resources. The scheduler determines availability of resources required for execution of an instruction based on the indication of future availability of the hardware resources, and dispatched the instruction for execution. The out-of-order execution processor also includes means to determine future completion of execution of source instructions a number of clock cycles before actual completion of execution.
    Type: Grant
    Filed: October 20, 1997
    Date of Patent: November 24, 1998
    Assignee: Intel Corporation
    Inventors: Glenn J. Hinton, Robert W. Martell, Michael A. Fetterman, David B. Papworth, James L. Schwartz
  • Patent number: 5826109
    Abstract: The present invention provides for executing load instructions with a processor having a non-blocking cache memory, wherein individual load operations are dispatched to the cache memory and the cache memory signals the prevent the load operation from being sent to external memory when the load operation misses the cache memory and there is already a currently pending bus cycle to the same cache line. This helps reduce bus traffic on the external bus.
    Type: Grant
    Filed: November 12, 1996
    Date of Patent: October 20, 1998
    Assignee: Intel Corporation
    Inventors: Jeffery M. Abramson, Haitham Akkary, Andrew F. Glew, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland, David B. Papworth, Robert W. Martell
  • Patent number: 5813037
    Abstract: A multi-port register file suitable for use in a reservation station in a superscalar microprocessor. The multi-port register is a static random access memory (SRAM) array which interleaves the data bits of the reservation station entries in a pair of storage cells. Because data may be associatively written to multiple entries within the SRAM cell array, a capacitance isolation mechanism including a plurality of inverters may be provided in data lines, such as writeback data lines, of the array. The isolation mechanism is situated so as to be shared by two interleaved cells within the SRAM array. The storage cells within the reservation station register may include at least one read port and a plurality of write or writeback ports coupled to a plurality of read enable and write enable lines. In one embodiment, cells of the SRAM array are exclusively read and thus a reduced sized sampling transistor may be used for the read ports.
    Type: Grant
    Filed: March 30, 1995
    Date of Patent: September 22, 1998
    Assignee: Intel Corporation
    Inventors: Robert W. Martell, Alexander P. Henstrom
  • Patent number: 5809325
    Abstract: An out-of-order execution processor comprising an execution unit, a storage unit and a scheduler is disclosed. The storage unit stores instructions awaiting availability of resources required for execution. The scheduler periodically determines whether resources required for executing each instruction are available, and if so, dispatches that instruction to the execution unit. The execution unit indicates future availability of hardware resources such as functional units and write back ports a number of clock cycles before actual availability of the hardware resources. The scheduler determines availability of resources required for execution of an instruction based on the indication of future availability of the hardware resources, and dispatched the instruction for execution. The out-of-order execution processor also includes means to determine future completion of execution of source instructions a number of clock cycles before actual completion of execution.
    Type: Grant
    Filed: July 9, 1996
    Date of Patent: September 15, 1998
    Assignee: Intel Corporation
    Inventors: Glenn J. Hinton, Robert W. Martell, Michael A. Fetterman, David B. Papworth, James L. Schwartz
  • Patent number: 5778210
    Abstract: A method and apparatus for recovering the state of a speculatively scheduled operation in a processor which cannot be executed at the speculated time allows components within the processor to begin the steps of dispatch and execution of operations based on the speculated return of data for the operations at a predetermined time. After these steps have begun for an operation, a signal is received by one or more of these components if the operation cannot be completed at the speculated time. If the operation cannot be completed at the speculated time then the operation is canceled, recovering the state of the operation prior to the beginning of the steps of dispatch and execution.
    Type: Grant
    Filed: January 11, 1996
    Date of Patent: July 7, 1998
    Assignee: Intel Corporation
    Inventors: Alexander P. Henstrom, Robert W. Martell
  • Patent number: D720001
    Type: Grant
    Filed: February 9, 2013
    Date of Patent: December 23, 2014
    Assignee: Graphic Products
    Inventors: Robert W. Martell, Richard Schoenert, Daniel Bruce Meyer, Stacy Foos, Aron Stephenson, Neal Blodgett, Tim Martin
  • Patent number: D778969
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: February 14, 2017
    Inventors: Daniel B. Meyer, Kasey Coussens, Timothy C. Martin, Robert W. Martell, Stacy H. Foos, Andrew J Sobiesczyk, Neal G. Blodgett