Abstract: A mechanism and method providing an early read operation of data associated with an instruction dispatched for execution to provide data dependency information in time to be used for scheduling subsequent instructions which may execute back-to-back in a pipeline microprocessor. The present invention provides the above functionality for instructions following single cycle instructions. The present invention provides immediate scheduling of instructions that are dependent on single cycle instructions. A reservation station holds the information pertaining to instructions that are to be scheduled for execution. The early read logic is implemented so that an address of a destination register associated with a dispatched single cycle instruction can be read from the associated entry of the reservation station early enough so as to be used and compared against the addresses of source registers of other instructions waiting to be scheduled (a CAM match).

Abstract: A method and apparatus for providing trace fault information to a trace fault handler. The trace fault information is evaluated prior to beginning execution of a micro code flow. The evaluated trace fault information is stored in a buffer and the micro code flow is executed. While the micro code flow is executing, if a micro code instruction of the micro code flow is executed that enables tracing, the trace fault information stored in the buffer is written to a data storage area. The data storage area is accessible to the trace fault handler.

Abstract: A reservation station includes a memory array in which micro-operations are stored at entry locations with an age representing a temporal ordering. Control circuitry resets the age of a new micro-operation, and increments the ages of previously stored micro-operations, when an entry is written into the array. Wired-OR circuitry is utilized to find the oldest age within the memory array, which is then broadcast through the array to generate a priority pointer that identifies a group of entries which contain an entry with the oldest age. Scheduling logic selects a ready entry in the group for dispatch to a port of the execution unit.

Abstract: Pipeline lengthening in functional units likely to be involved in a writeback conflict is implemented to avoid conflicts. Logic circuitry is provided for comparing the depths of two concurrently executing execution unit pipelines to determine if a conflict will develop. When it appears that two execution units will attempt to write back at the same time, the execution unit having a shorter pipeline will be instructed to add a stage to its pipeline, storing its result in a delaying buffer for one clock cycle. After the conflict has been resolved, the instruction to lengthen the pipeline of a given functional unit will be rescinded. Multistage execution units are designed to signal a reservation station to delay the dispatch of various instructions to avoid conflicts between execution units.

Abstract: An out-of-order execution processor comprising an execution unit, a storage unit and a scheduler is disclosed. The storage unit stores instructions awaiting availability of resources required for execution. The scheduler periodically determines whether resources required for executing each instruction are available, and if so, dispatches that instruction to the execution unit. The execution unit indicates future availability of hardware resources such as functional units and write back ports a number of clock cycles before actual availability of the hardware resources. The scheduler determines availability of resources required for execution of an instruction based on the indication of future availability of the hardware resources, and dispatched the instruction for execution. The out-of-order execution processor also includes means to determine future completion of execution of source instructions a number of clock cycles before actual completion of execution.

Abstract: Maximum throughput or "back-to-back" scheduling of dependent instructions in a pipelined processor is achieved by maximizing the efficiency in which the processor determines the availability of the source operands of a dependent instruction and provides those operands to an execution unit executing the dependent instruction. These two operations are implemented through a number of mechanisms. One mechanism for determining the availability of source operands, and hence the readiness of a dependent instruction for dispatch to an available execution unit, relies on the early setting of a source valid bit during allocation when a source operand is a retired or immediate value. This allows the ready logic of a reservation station to begin scheduling the instruction for dispatch.

Abstract: An instruction dispatch circuit is disclosed that improves instruction execution throughput for a processor. The instruction dispatch circuit comprises an instruction buffer with a plurality of instruction entries and a content addressable memory array having at least one cam entry corresponding to each instruction entry. Each cam entry stores at least one source tag for the corresponding instruction entry. The content addressable memory array matches to a result tag from an execution circuit over a result bus, wherein the execution circuit transfers the result tag over the result bus at least one clock cycle before transferring a corresponding result data value over the result bus. Each cam entry generates a cam match signal used to determine whether data dependent instruction are ready for dispatch.

Abstract: Entries in a reservation station are efficiently scanned to find data-ready instructions for dispatch. A pseudo-FIFO scheduling approach is implemented wherein, rather than scanning every entry in the reservation station, the reservation station is segmented into groups of entries with each entry being scanned to determine which has the oldest entry in it. It is from the group of entries having the oldest entry that a ready pointer is cycled to search for data-ready instructions for dispatch to waiting execution units.