Patents by Inventor Robert W. Wu

Robert W. Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5986875
    Abstract: A puncture resistant electrostatic chuck (20) is described. The chuck (20) comprises at least one electrode (25); and a composite insulator (30) covering the electrode. The composite insulator comprises a matrix material having a conformal holding surface (50) capable of conforming to the substrate (35) under application of an electrostatic force generated by the electrode to reduce leakage of heat transfer fluid held between the substrate and the holding surface. A hard puncture resistant layer, such a layer of fibers or an aromatic polyamide layer, is positioned below the holding surface (50) and is sufficiently hard to increase the puncture resistance of the composite insulator.
    Type: Grant
    Filed: January 29, 1998
    Date of Patent: November 16, 1999
    Assignee: Applied Materials, Inc.
    Inventors: Arik Donde, Hyman J. Levinstein, Robert W. Wu, Andreas Hegedus, Edwin C. Weldon, Shamouil Shamouilian, Jon T. Clinton, Surinder S. Bedi
  • Patent number: 5965463
    Abstract: A low-temperature process for selectively etching oxide with high selectivity over silicon in a high-density plasma reactor. The principal etching gas is a hydrogen-free fluorocarbon, such as C.sub.2 F.sub.6 or C.sub.4 F.sub.8, to which is added a silane or similar silicon-bearing gas, e.g., the monosilane SiH.sub.4. The fluorocarbon and silane are added in a ratio within the range of 2 to 5, preferably 2.5 to 3. The process provides high polysilicon selectivity, high photoresist facet selectivity, and steep profile angles. Selectivity is enhanced by operating at high flow rates. Silicon tetrafluoride may be added to enhance the oxide etching rate. The process may operate at temperatures of chamber parts below 180.degree. C. and even down to 120.degree. C. The process enables the fabrication of a bi-level contact structure with a wide process window.
    Type: Grant
    Filed: July 3, 1997
    Date of Patent: October 12, 1999
    Assignee: Applied Materials, Inc.
    Inventors: Chunshi Cui, Robert W. Wu, Gerald Zheyao Yin
  • Patent number: 5910221
    Abstract: A plasma reactor, for example, for processing a semiconductor wafer, in which parts of the chamber are formed of multiple pieces of silicon carbide that have been bonded together. The bonding may be performed by diffusion bonding or by using a bonding agent such as polyimide. These silicon carbide parts typically face and define a plasma region. Preferably, the surface facing the plasma is coated with a silicon carbide film, such as that deposited by chemical vapor deposition, which is more resistant to erosion by the plasma. Advantageously, the different parts are formed with different electrical resistivities consistent with forming an advantageous plasma.
    Type: Grant
    Filed: June 18, 1997
    Date of Patent: June 8, 1999
    Assignee: Applied Materials, Inc.
    Inventor: Robert W. Wu
  • Patent number: 5904778
    Abstract: A composite silicon carbide article and its method of making in which a surface layer or film of silicon carbide is deposited, for example by chemical vapor deposition (CVD), over a free standing silicon carbide substrate, as is formed by bulk methods such as sintering and hot pressing. The article is advantageously used in a plasma reactor, especially an oxide etcher for semiconductor fabrication, and may be any of several parts including the chamber wall, chamber roof, or collar around the wafer. The bulk SiC provides an inexpensive and strong support structure of perhaps a complex shape while the CVD SiC film has advantages for plasma processing and may be tailored to particular uses. The composite SiC structure is particularly useful in that the electrical conductivities of the bulk SiC and film SiC may be separately controlled so as to provide, among many possibilities, a grounding plane, a window for RF electromagnetic radiation, or both.
    Type: Grant
    Filed: July 26, 1996
    Date of Patent: May 18, 1999
    Assignee: Applied Materials, Inc.
    Inventors: Hao A Lu, Nianci Han, Gerald Z Yin, Robert W Wu
  • Patent number: 5891350
    Abstract: A method of adjusting the cathode DC bias in a plasma chamber for fabricating semiconductor devices. A dielectric shield is positioned between the plasma and a selected portion of the electrically grounded components of the chamber, such as the electrically grounded chamber wall. The cathode DC bias is adjusted by controlling one or more of the following parameters: (1) the surface area of the chamber wall or other grounded components which is blocked by the dielectric shield; (2) the thickness of the dielectric; (3) the gap between the shield and the chamber wall; and (4) the dielectric constant of the dielectric material. In an apparatus aspect, the invention is a plasma chamber for fabricating semiconductor devices having an exhaust baffle with a number of sinuous passages. Each passage is sufficiently long and sinuous that no portion of the plasma within the chamber can extend beyond the outlet of the passage.
    Type: Grant
    Filed: June 20, 1996
    Date of Patent: April 6, 1999
    Assignee: Applied Materials, Inc.
    Inventors: Hong Ching Shan, Evans Yip Lee, Michael D Welch, Robert W Wu, Bryan Pu, Paul Ernest Luscher, James David Carducci, Richard Blume
  • Patent number: 5729423
    Abstract: A puncture resistant electrostatic chuck (20) is described. The chuck (20) comprises at least one electrode (25); and a composite insulator (30) covering the electrode. The composite insulator comprises a matrix material having a conformal holding surface (50) capable of conforming to the substrate (35) under application of an electrostatic force generated by the electrode to reduce leakage of heat transfer fluid held between the substrate and the holding surface. A hard puncture resistant layer, such a layer of fibers or an aromatic polyamide layer, is positioned below the holding surface (50) and is sufficiently hard to increase the puncture resistance of the composite insulator.
    Type: Grant
    Filed: November 25, 1996
    Date of Patent: March 17, 1998
    Assignee: Applied Materials, Inc.
    Inventors: Arik Donde, Hyman J. Levinstein, Robert W. Wu, Andreas Hegedus, Edwin C. Weldon, Shamouil Shamouilian, Jon T. Clinton, Surinder S. Bedi
  • Patent number: 5110712
    Abstract: A system for integrating a composite dielectric layer in an integrated circuit to facilitate fabrication of a high density multi-level interconnect with external contacts. The composite dielectric layer comprises of a polymer layer which normally comprises a polyimide that is deposited using conventional spin-deposit techniques to form a planarized surface for deposition of an inorganic layer typically comprising silicon dioxide or silicon nitride. The inorganic layer is etched using standard photoresist techniques to form an inorganic mask for etching the polymer layer. A previously deposited inorganic layer functions as an etch stop to allow long over etches to achieve full external contacts which, in turn, allows high density interconnect systems on multiple levels.
    Type: Grant
    Filed: April 25, 1990
    Date of Patent: May 5, 1992
    Assignee: Hewlett-Packard Company
    Inventors: Daniel D. Kessler, Robert W. Wu, Christopher C. Beatty, Mark D. Crook