Patents by Inventor Robert Walker

Robert Walker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210271492
    Abstract: Methods and systems for accessing conflicting frameworks and classes are presented. In some embodiments, a conflicting frameworks computing platform may receive an application classloader corresponding to a mobile application. The application classloader may indicate one or more child application-defined classloaders. Subsequently, the conflicting frameworks computing platform may create a framework-defined classloader comprising a first class that conflicts with a second class in the one or more child application-defined classloaders. Further, the conflicting frameworks computing platform may create a framework-termination classloader. The framework-termination classloader may be a parent classloader of the framework-defined classloader. Next, the conflicting frameworks computing platform may replace, using a reflection function, the application classloader with a new application classloader.
    Type: Application
    Filed: May 18, 2021
    Publication date: September 2, 2021
    Inventor: James Robert Walker
  • Publication number: 20210266305
    Abstract: A secure control system includes a network of multiplexers that control end/field devices of an infrastructure system, such as an electric power grid. The multiplexers have a default secure lockdown state that prevents remote access to data on the multiplexers and prevents modification of software or firmware of the multiplexer. One or more of the multiplexers include a physical authentication device that confirms the physical proximity of a trusted individual when remote access is requested. A user accesses the network and one of the multiplexers remotely by way of login credentials. The trusted individual confirms the identity of the remote user and operates the physical authentication device connected with and in proximity to that multiplexer, thereby confirming that the remote user can be trusted to access data and reconfigure the multiplexers.
    Type: Application
    Filed: April 21, 2021
    Publication date: August 26, 2021
    Inventors: Michael David Kramarczyk, Emmanuel Duvelson, Robert Walker
  • Patent number: 11087517
    Abstract: In particular embodiments, a 2D representation of an object may be provided. A first method may comprise: receiving sketch input identifying a target position for a specified portion of the object; computing a deformation for the object within the context of a character rig specification for the object; and displaying an updated version of the object. A second method may comprise detecting sketch input; classifying the sketch input, based on the 2D representation, as an instantiation of the object; instantiating the object using a 3D model of the object; and displaying a 3D visual representation of the object.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: August 10, 2021
    Assignees: Disney Enterprises, Inc., ETH Zürich (Eidgenössische Technische Hochschule Zürich)
    Inventors: Robert Walker Sumner, Maurizio Nitti, Stelian Coros, Bernhard Thomaszewski, Fabian Andreas Hahn, Markus Gross, Frederik Rudolf Mutzel
  • Publication number: 20210223999
    Abstract: Commands in a command queue are received and scheduled. For each of the commands, scheduling includes determining an age of a command based on an entrance time of the command in the command queue. When the age of the command satisfies a first threshold, marking all other commands in the command queue as not issuable when the command is a deterministic command, and marking all other commands in the command queue as not issuable when the command is a non-deterministic command and the intermediate command queue is not empty. Scheduling the command further includes determining whether the command is a read command and marking the command as not issuable when the command is a non-deterministic read command and the intermediate command queue is empty.
    Type: Application
    Filed: April 6, 2021
    Publication date: July 22, 2021
    Inventors: Patrick A. La Fratta, Robert Walker
  • Publication number: 20210227361
    Abstract: A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The system then generating, using an internal address decoder, an internal address based on the input address, the interleaving factor, and the number of first addressable units. Generating the internal address includes: determining a lower address value by extracting lower bits of the internal address, determining an upper address value by extracting upper bits of the internal address, and adding the lower address value to the upper address value to generate the internal address. Using an internal power-of-two address boundary decoder and the internal address, the system then generating a second addressable unit address, a third addressable unit address, a fourth addressable unit address, and a fifth addressable unit address.
    Type: Application
    Filed: March 17, 2021
    Publication date: July 22, 2021
    Inventors: Patrick A. La Fratta, Robert Walker, Chandrasekhar Nagarajan
  • Patent number: 11048527
    Abstract: Methods and systems for accessing conflicting frameworks and classes are presented. In some embodiments, a conflicting frameworks computing platform may receive an application classloader corresponding to a mobile application. The application classloader may indicate one or more child application-defined classloaders. Subsequently, the conflicting frameworks computing platform may create a framework-defined classloader comprising a first class that conflicts with a second class in the one or more child application-defined classloaders. Further, the conflicting frameworks computing platform may create a framework-termination classloader. The framework-termination classloader may be a parent classloader of the framework-defined classloader. Next, the conflicting frameworks computing platform may replace, using a reflection function, the application classloader with a new application classloader.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: June 29, 2021
    Assignee: Citrix Systems, Inc.
    Inventor: James Robert Walker
  • Patent number: 11020620
    Abstract: A fire protection external vehicle cover including a plurality of panels of a fire retardant material or textile. Each panel is configured to cover an adjacent portion of the cabin of the vehicle; with one or more panels including a retention mechanism to secure the panels by gripping between closed doors and door frames of the cabin. A storage and deployment mechanism is configured to store and deploy the cover from one or more locations on the vehicle; wherein in operation, when deployed, the cover forms an enclosure over the cabin thereby protecting external surfaces of the cabin and thus its occupants and an internal lining of the vehicle from exposure to radiant heat, burning embers and flames if the vehicle is moving through or becomes trapped in a fire.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: June 1, 2021
    Inventors: Robert James Walker, Matthew Robert Walker
  • Publication number: 20210157510
    Abstract: Various embodiments described herein provide for execution of a memory function within a memory sub-system. For example, some embodiments provide for execution of certain memory-related functions internally within the memory sub-system, at the request of a host system, using one or more memory access operations (e.g., direct memory access operations) performed internally within the memory sub-system.
    Type: Application
    Filed: November 25, 2019
    Publication date: May 27, 2021
    Inventors: Dhawal Bavishi, Robert Walker
  • Patent number: 11016885
    Abstract: A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The system then generating, using an internal address decoder, an internal address based on the input address, the interleaving factor, and the number of first addressable units. Generating the internal address includes: determining a lower address value by extracting lower bits of the internal address, determining an upper address value by extracting upper bits of the internal address, and adding the lower address value to the upper address value to generate the internal address. Using an internal power-of-two address boundary decoder and the internal address, the system then generating a second addressable unit address, a third addressable unit address, a fourth addressable unit address, and a fifth addressable unit address.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: May 25, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Patrick A. La Fratta, Robert Walker, Chandrasekhar Nagarajan
  • Patent number: 11005831
    Abstract: A secure control system includes a network of multiplexers that control end/field devices of an infrastructure system, such as an electric power grid. The multiplexers have a default secure lockdown state that prevents remote access to data on the multiplexers and prevents modification of software or firmware of the multiplexer. One or more of the multiplexers include a physical authentication device that confirms the physical proximity of a trusted individual when remote access is requested. A user accesses the network and one of the multiplexers remotely by way of login credentials. The trusted individual confirms the identity of the remote user and operates the physical authentication device connected with and in proximity to that multiplexer, thereby confirming that the remote user can be trusted to access data and reconfigure the multiplexers.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: May 11, 2021
    Assignee: Hubbell Incorporated
    Inventors: Michael David Kramarczyk, Emmanuel Duvelson, Robert Walker
  • Patent number: 10990321
    Abstract: Commands in a command queue are received and scheduled. For each of the commands, scheduling includes determining an age of a command based on an entrance time of the command in the command queue. When the age of the command satisfies a first threshold, marking all other commands in the command queue as not issuable when the command is a deterministic command, and marking all other commands in the command queue as not issuable when the command is a non-deterministic command and the intermediate command queue is not empty. Scheduling the command further includes determining whether the command is a read command and marking the command as not issuable when the command is a non-deterministic read command and the intermediate command queue is empty.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: April 27, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Patrick A. La Fratta, Robert Walker
  • Patent number: 10970247
    Abstract: An internal processor of a memory device configured to selectively execute instructions in parallel, for example. One such internal processor includes a plurality of arithmetic logic units (ALUs), each connected to conditional masking logic, and each configured to process conditional instructions. A condition instruction may be received by a sequencer of the memory device. Once the condition instruction is received, the sequencer may enable the conditional masking logic of the ALUs. The sequencer may toggle a signal to the conditional masking logic such that the masking logic masks certain instructions if a condition of the condition instruction has been met, and masks other instructions if the condition has not been met. In one embodiment, each ALU in the internal processor may selectively perform instructions in parallel.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: April 6, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Robert Walker
  • Patent number: 10959443
    Abstract: A liquid treatment device includes a base with a power source, a UV-LED module for providing UV-B or UV-C light to liquid, an LED for providing visible light, and a processor for selectively powering the UV-LED module and the LED, and having a UV transmissive material above the UV-LED module for allowing the UV-B or UV-C band light from the UV-LED module to be transmitted from the base housing, and a liquid storage housing removably coupled to the base housing with a storage portion configured to hold liquid and having a bottom portion comprising a UV transmissive material for allowing the UV-B or UV-C band light from the UV-LED module to be transmitted into the liquid, and an output coupled for restricting outflow of the liquid from the storage portion.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: March 30, 2021
    Assignee: LARQ, INC.
    Inventors: Yitao Liao, Robert Walker, Doug Collins
  • Publication number: 20210080653
    Abstract: An optical waveguide crosspoint comprising first and second single multimode interference sections, each single multimode interference section comprising an input face, an output face and sidewalls extending therebetween, the distance between the input face and output face for each single multimode interference section being the; length of the multimode interference section, the lengths of the first and second multimode interference sections being L1 and L2 respectively; at least one primary input optical waveguide connected to the input face of the first single multimode interference section; at least one primary output optical waveguide connected to the output face of the first single multimode interference section; the first single multimode interference section comprising a symmetry axis extending from the center of the input face to the center of the output face; at least one secondary input optical waveguide connected to the input face of the second single multimode interference section; at least one se
    Type: Application
    Filed: December 19, 2017
    Publication date: March 18, 2021
    Applicant: Axenic Limited
    Inventor: Robert Walker
  • Publication number: 20210081338
    Abstract: Memory devices, systems and methods are described, such as those including a dynamically configurable channel depth. Devices, systems and methods are described that adjust channel depth based on hardware and/or software requirements. One such device provides for virtual memory operations where a channel depth is adjusted for the same physical memory region responsive to requirements of different memory processes.
    Type: Application
    Filed: November 16, 2020
    Publication date: March 18, 2021
    Inventor: Robert Walker
  • Publication number: 20210072050
    Abstract: Provided is an optical waveguide with an inscribed Bragg grating, where the Bragg grating is stable at high temperature, has low scattering loss and high reflectivity. Also provided is a method for inscribing a Bragg grating in an optical waveguide, the method comprising irradiating the optical waveguide with electromagnetic radiation from an ultrashort pulse duration laser of sufficient intensity to cause a permanent change in an index of refraction within a core of the optical waveguide, where the irradiating step is terminated prior to erasure of a Bragg resonance, and heating the optical waveguide to a temperature and for a duration sufficient to substantially remove a non-permanent grating formed in the optical waveguide by the irradiating step.
    Type: Application
    Filed: November 19, 2020
    Publication date: March 11, 2021
    Inventors: Dan GROBNIC, Stephen MIHAILOV, Robert WALKER, Ping LU, Huimin DING, David COULAS, Cyril HNATOVSKY
  • Patent number: 10936772
    Abstract: Configuration data for an integrated circuit may be generated using logic design equipment to implement a logic design on the integrated circuit. The equipment may perform multiple rounds of incremental physical synthesis, incremental timing analysis, and incremental legalization operations. Each round may involve performing multiple different physical synthesis transforms on the design that are individually rejected until transforms that satisfy legality constraints and improve timing for the logic design are found and incorporated into the netlist. The configuration data may then be generated using the netlist. In this way, the logic design may be incrementally altered and verified during the physical synthesis process. This prevents the need for rejecting or accepting an entire batch logic changes to the netlist even when only some of the changes are non-ideal, thus optimizing circuit performance as well as the compile time required to implement the logic design on the integrated circuit.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: March 2, 2021
    Assignee: Altera Corporation
    Inventors: Mahesh A. Iyer, Robert Walker, Vasudeva M. Kamath
  • Publication number: 20210042219
    Abstract: Apparatuses and methods for adaptive control of memory are disclosed. One example apparatus includes a memory translation unit configured to receive a memory access request including a requested address and to determine a mapping state of a region of a memory associated with the requested address. The memory translation unit further configured to provide a mapped address to the memory. The mapped address is selected from one of the requested address or a translated requested address based on the state of the region of the memory associated with the requested address.
    Type: Application
    Filed: October 23, 2020
    Publication date: February 11, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: David A. Roberts, J. Thomas Pawlowski, Robert Walker
  • Patent number: 10908896
    Abstract: Methods and systems for developing, modifying, and distributing software applications for enterprise systems are described herein. A software component, such as a native mobile application or a template application, may be modified into a managed mobile application, and metadata associated with the managed mobile application may be generated. The managed application and associated metadata may be provided to one or more application stores, such as public application stores and/or enterprise application stores. Managed applications and/or associated metadata may be retrieved by computing devices from public application stores and/or enterprise application stores, and may be executed as managed applications in an enterprise system.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: February 2, 2021
    Assignee: Citrix Systems, Inc.
    Inventors: Zhongmin Lang, Gary Barton, James Robert Walker, Vipin Aravindakshan
  • Publication number: 20210019928
    Abstract: Techniques are disclosed for learning a machine learning model that maps control data, such as renderings of skeletons, and associated three-dimensional (3D) information to two-dimensional (2D) renderings of a character. The machine learning model may be an adaptation of the U-Net architecture that accounts for 3D information and is trained using a perceptual loss between images generated by the machine learning model and ground truth images. Once trained, the machine learning model may be used to animate a character, such as in the context of previsualization or a video game, based on control of associated control points.
    Type: Application
    Filed: July 15, 2019
    Publication date: January 21, 2021
    Inventors: Dominik Tobias BORER, Martin GUAY, Jakob Joachim BUHMANN, Robert Walker SUMNER