Abstract: A coupled inductor structure includes a first three-dimensional inductor structure and a second three-dimensional folded inductor structure. At least a portion of the first three-dimensional folded inductor structure is located within a volume bounded by the second three-dimensional folded inductor structure. By nesting the first three-dimensional folded inductor structure within the second three-dimensional folded inductor structure, a variety of coupling factors can be achieved while minimizing the size of the coupled inductor structure.

Abstract: A power amplifier system is disclosed. The power amplifier system includes a power amplifier having a first signal input and a first signal output and a main bias circuitry configured to provide a first portion of a first bias signal to the power amplifier through a first bias output coupled to the first signal input. Further included is peak bias circuitry that is configured to provide a second portion of the first bias signal to the power amplifier through a second bias output coupled to the first signal input, wherein the first portion of the first bias signal is greater than the second portion of the first bias signal over a first input power range and the second portion of the first bias signal is greater than the first portion of the first bias signal over a second input power range that is greater than the first input power range.

Abstract: A broadband power amplifier circuit is provided. The broadband power amplifier circuit includes an amplifier circuit configured to amplify a radio frequency (RF) signal to an output power based on a bias voltage and a supply voltage. Given that the output power of the RF signal may rise and fall from time to time, the broadband power amplifier circuit is configured to opportunistically increase or decrease the bias voltage in a defined future time (e.g., a future time slot or a future symbol duration) based on the output power in the defined future time. When necessary, the broadband power amplifier may be further configured to adjust the supply voltage and/or attenuate the RF signal based on the output power. As such, it may be possible to maintain class-A operation mode for the amplifier circuit. As a result, the amplifier circuit may maintain linearity and avoid memory effect with improved efficiency.

Abstract: Novel and useful quantum structures having a continuous fully depleted well with control gates that form two quantum dot on either side of the gate. Appropriate potentials are applied to the well and control gate to control quantum tunneling between quantum dots thereby enabling quantum operations to occur. Qubits are realized by modulating applied gate potential to control tunneling through a quantum transport path between two or more sections of the well. Complex structures with a higher number of quantum dots per continuous well and a larger number of wells can be fabricated. Both planar and 3D FinFET semiconductor processes are used to build well to gate and well to well tunneling quantum structures. An injection device permits tunneling of a single quantum particle from a classic side to a quantum side of the device. Detection interface devices detect the presence or absence of a particle destructively or nondestructively.

Abstract: A novel and useful fully integrated quantum computer containing both quantum core circuitry and associated classical electronic control circuits on the same monolithic die. The integrated quantum computer avoids ESD loading on the quantum structures and minimizes the need for long interconnects with resultant large parasitic inductances and capacitances. Such parasitics reduce the maximum operating frequency of the realized quantum core structures. A cryostat unit functions to provide several temperatures to the quantum computer including a temperature to cool the quantum core to approximately 4° K and the interface SoC to 77° K. Alternatively, the interface circuitry is also integrated with the main QPU on the same die. A programmable pattern generator executes sequences of instructions that control the quantum core. In accordance with the sequences, a pulse generator functions to generate the control signals that are input to the quantum core to perform quantum operations.

Abstract: The present disclosure relates to a semiconductor package with reduced parasitic coupling effects, and a process for making the same. The disclosed semiconductor package includes a thinned flip-chip die and a first mold compound component with a dielectric constant no more than 7. The thinned flip-chip die includes a back-end-of-line (BEOL) layer with an upper surface that includes a first surface portion and a second surface portion surrounding the first surface portion, a device layer over the upper surface of the BEOL layer, and a buried oxide (BOX) layer over the device layer. The BEOL layer includes a first passive device and a second passive device, which are underlying the first surface portion and not underlying the second surface portion. Herein, the first mold compound component extends through the BOX layer and the device layer to the first surface portion.

Abstract: A novel and useful modified semiconductor process having staircase active well shapes that provide variable distances between pairs of locations (i.e. quantum dots) resulting in modulation of the quantum interaction strength from weak/negligible at large separations to moderate and then strong at short separations. To achieve a modulation of the distance between pairs of locations, diagonal, lateral, and vertical quantum particle/state transport is employed. As examples, both implementations of semiconductor quantum structures with tunneling through an oxide layer and with tunneling through a local well depleted region are disclosed. These techniques are applicable to both planar semiconductor processes and 3D (e.g. Fin-FET) semiconductor processes. Optical proximity correction is used to accommodate the staircase well layers. Each gate control circuit in the imposer circuitry functions to control more than one set of control gates.

Abstract: A low-noise amplifier system is disclosed. The low-noise amplifier system includes a low-noise amplifier having an input node and an output node in a receive path and a capacitance equalization network coupled to the output node. Compensation capacitance of the capacitance equalization network sums with non-linear capacitance of the low-noise amplifier such that a total capacitance at the output node varies by no more than ±5% over an output voltage range within voltage headroom limits of the low-noise amplifier for a given supply voltage of the low-noise amplifier. In at least some exemplary embodiments, the compensation capacitance of the capacitance equalization network is a function of output signal voltage at the output node.

Abstract: The present disclosure relates to a transmission line structure embedded in a back-end-of-line (BEOL) body that has a cavity. The transmission line structure includes a signal transmission line, a ground plane and a shielding line. The signal transmission line and the first shielding line are formed on a same metallization level, and the ground plane is formed underneath and electrically connected to the first shielding line. A side surface of the signal transmission line and a side surface of the first shielding line, which faces the side surface of the signal transmission line, are exposed to the cavity of the BEOL body, and not covered by any high resistivity conductive coating.

Abstract: The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.

Abstract: A novel and useful topological, scalable, and reprogrammable quantum computing machine having one or more quasi-unidimensional chord lines along which the movement of a particle is constrained. The unidimensional passage has localized energy levels that can be controlled with classic electronics. The chord line has two or more quantum dots between which a quasi-unidimensional channel is formed for the particle to travel from one qdot to the other. The tunneling path may be polysilicon, metal, thin oxide, or induced depletion region. The chord line can be in a two-dimensional space for a planar process or in a three-dimensional space with multiple layers of signal processing for a three dimensional process. A quantum structure has semiconductor dots with a layer that provides the chord line for the quantum particle evolution to occur from one dot to the other. The various layers may include polysilicon, metal, thin oxide, or induced depletion region either fully overlapped or partially overlapped.

Abstract: A method for use in populating a user profile comprises the steps of: determining that a first person within a database of people is associated with a given award within a database of awards; determining that a first project within a database of projects is associated with the given award within a database of awards; and populating the profile for the first person with information associated with the first project.

Abstract: The present disclosure relates to a semiconductor package with reduced parasitic coupling effects, and a process for making the same. The disclosed semiconductor package includes a thinned flip-chip die and a first mold compound component with a dielectric constant no more than 7. The thinned flip-chip die includes a back-end-of-line (BEOL) layer with an upper surface that includes a first surface portion and a second surface portion surrounding the first surface portion, a device layer over the upper surface of the BEOL layer, and a buried oxide (BOX) layer over the device layer. The BEOL layer includes a first passive device and a second passive device, which are underlying the first surface portion and not underlying the second surface portion. Herein, the first mold compound component extends through the BOX layer and the device layer to the first surface portion.

Abstract: Power amplifier (PA) output memory neutralization is disclosed, using baseband input/output (I/O) capacitance current compensation. Radio frequency (RF) PAs experience I/O memory effects when used with envelope tracking supply modulation schemes. Envelope tracking supply modulation results in a nonlinear variation of the I/O capacitance. Traditional approaches compensate for such effects with a current provided by a bias circuit which is band-limited. This results in memory effects which distort the amplified signal, becoming more significant as the modulation bandwidth increases. An RF communications system according to embodiments disclosed herein mitigates such memory effects by compensating for the non-linear effect of the I/O capacitance in an RF PA.

Abstract: A power amplifier apparatus supporting reverse intermodulation product (rIMD) cancellation is provided. The power amplifier apparatus includes an amplifier circuit configured to amplify and output a radio frequency (RF) signal for transmission via an antenna port. The antenna port may receive a reverse interference signal, which may interfere with the RF signal to create a rIMD(s) that can fall within an RF receive band(s). A reverse coupling circuit is provided in the power amplifier apparatus to generate an interference cancellation signal based on the reverse interference signal. The amplifier circuit is configured to amplify the interference cancellation signal and the RF signal to create an intermodulation product(s) to suppress the rIMD(s) to a determined threshold. By suppressing the rIMD(s) in the power amplifier apparatus, it is possible to support concurrent transmissions and receptions in a number of RF spectrums while in compliance with stringent regulatory spurious emissions (SEM) requirements.

Abstract: A novel and useful controlled quantum shift register for transporting particles from one quantum dot to another in a quantum structure. The shift register incorporates a succession of qdots with tunneling paths and control gates. Applying appropriate control signals to the control gates, a particle or a split quantum state is made to travel along the shift register. The shift register also includes ancillary double interaction where two pairs of quantum dots provide an ancillary function where the quantum state of one pair is replicated in the second pair. The shift register also provides bifurcation where an access path is split into two or more paths. Depending on the control pulse signals applied, quantum dots are extended into multiple paths. Control of the shift register is provided by electric control pulses. An optional auxiliary magnetic field provides additional control of the shift register.

Abstract: A novel and useful controlled quantum shift register for transporting particles from one quantum dot to another in a quantum structure. The shift register incorporates a succession of qdots with tunneling paths and control gates. Applying appropriate control signals to the control gates, a particle or a split quantum state is made to travel along the shift register. The shift register also includes ancillary double interaction where two pairs of quantum dots provide an ancillary function where the quantum state of one pair is replicated in the second pair. The shift register also provides bifurcation where an access path is split into two or more paths. Depending on the control pulse signals applied, quantum dots are extended into multiple paths. Control of the shift register is provided by electric control pulses. An optional auxiliary magnetic field provides additional control of the shift register.

Abstract: The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.

Abstract: Embodiments of the disclosure relate to a three-dimensional (3D) inductor-capacitor (LC) circuit. The 3D LC circuit includes an inductor formed by a conductive ribbon of a defined height and a conductive sleeve conductively coupled to the conductive ribbon. The conductive sleeve and the conductive ribbon can generate a built-in capacitance(s) for the 3D LC circuit. In examples discussed herein, the conductive ribbon can also help reduce the skin effect of the inductor by distributing an electrical current across the defined height of the conductive ribbon. By generating the built-in capacitance(s) and distributing the electrical current across the defined height of the conductive ribbon, it is possible to reduce current crowding and improve quality factor (Q-factor) of the 3D LC circuit. As a result, it is possible to couple one or more 3D LC circuits to form a high performance radio frequency (RF) filter(s) for the fifth-generation (5G) wireless communication systems.

Abstract: Embodiments of an apparatus that includes a substrate and an inductor residing in the substrate are disclosed. In one embodiment, the inductor is formed as a conductive path that extends from a first terminal to a second terminal. The conductive path has a shape corresponding to a two-dimensional (2D) lobe laid over a three-dimensional (3D) volume. Since the shape of the conductive path corresponds to the 2D lobe laid over a 3D volume, the magnetic field generated by the inductor has magnetic field lines that are predominately destructive outside the inductor and magnetic field lines that are predominately constructive inside the inductor. In this manner, the inductor can maintain a high quality (Q) factor while being placed close to other components.