Patents by Inventor Robert Warren Sherburne, Jr.

Robert Warren Sherburne, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FLEXIBLE MULTI-PROCESSING SYSTEM
    Publication number: 20120173864
    Abstract: A processor includes a scalar computation unit; a vector co-processor coupled to the scalar computation unit; and one or more function-specific engines coupled to the scalar computation unit, the engines adapted to minimize data exchange penalties by processing small in-out bit slices.
    Type: Application
    Filed: January 2, 2012
    Publication date: July 5, 2012
    Applicant: Intellectual Ventures I LLC
    Inventors: Dominik J. Schmidt, Robert Warren Sherburne, JR.
  • Methods and apparatus for processing scalar and vector instructions
    Patent number: 8090928
    Abstract: In one embodiment of the present invention, a processor includes a scalar computation unit; a vector co-processor coupled to the scalar computation unit; and one or more function-specific engines coupled to the scalar computation unit, where the engines are adapted to minimize data exchange penalties by processing small in-out bit slices.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: January 3, 2012
    Assignee: Intellectual Ventures I LLC
    Inventors: Dominik J. Schmidt, Robert Warren Sherburne, Jr.
  • Clocking system including a clock controller that uses buffer feedback to vary a clock frequency
    Patent number: 7398414
    Abstract: A low power reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; one or more clock controllers having clock outputs coupled to the clock inputs of the processing units, the controller operating varying the clock frequency of each processing unit to optimize speed and processing power for a task; and a high-density memory array core coupled to the processing units.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: July 8, 2008
    Assignee: Gallitzin Allegheny LLC
    Inventor: Robert Warren Sherburne, Jr.
  • Low power clocking systems and methods
    Patent number: 7139921
    Abstract: A low power reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; and a controller having a plurality of clock outputs each coupled to a respective clock input of one of the processing units, the controller varying the clock frequency of each processing unit to optimize power consumption and processing power for a task.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: November 21, 2006
    Inventor: Robert Warren Sherburne, Jr.
  • Low power clocking systems and methods
    Patent number: 6993669
    Abstract: A low power a reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; and a controller having a plurality of clock outputs each coupled to the clock inputs of the processing units, the controller varying the clock frequency of each processing unit to optimize power consumption and processing power for a task.
    Type: Grant
    Filed: April 18, 2001
    Date of Patent: January 31, 2006
    Assignee: Gallitzin Allegheny LLC
    Inventor: Robert Warren Sherburne, Jr.
  • Low power reconfigurable systems and methods
    Patent number: 6990598
    Abstract: A low power reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; one or more clock controllers having clock outputs coupled to the clock inputs of the processing units, the controller operating varying the clock frequency of each processing unit to optimize speed and processing power for a task; and a high-density memory array core coupled to the processing units.
    Type: Grant
    Filed: March 21, 2001
    Date of Patent: January 24, 2006
    Assignee: Gallitzin Allegheny LLC
    Inventor: Robert Warren Sherburne, Jr.
  • Method and device for modifying the memory contents of and reprogramming a memory
    Publication number: 20020184546
    Abstract: A low power a reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; and a controller having a plurality of clock outputs each coupled to the clock inputs of the processing units, the controller varying the clock frequency of each processing unit to optimize power consumption and processing power for a task.
    Type: Application
    Filed: April 18, 2001
    Publication date: December 5, 2002
    Inventor: Robert Warren Sherburne, Jr