Abstract: The present invention provides various combinations of genetic modifications to a transformed host cell that provide increase conversion of carbon to a chemical product. The present invention also provides methods of fermentation and methods of making various chemical products.

Abstract: The present invention provides various combinations of genetic modifications to a transformed host cell that provide increase conversion of carbon to a chemical product. The present invention also provides methods of fermentation and methods of making various chemical products.

Abstract: The present invention provides various combinations of genetic modifications to a transformed host cell that provide increase conversion of carbon to a chemical product. The present invention also provides methods of fermentation and methods of making various chemical products.

Abstract: The present invention provides various combinations of genetic modifications to a transformed host cell that provide increase conversion of carbon to a chemical product. The present invention also provides methods of fermentation and methods of making various chemical products.

Abstract: The present invention provides various combinations of genetic modifications to a transformed host cell that provide increase conversion of carbon to a chemical product. The present invention also provides methods of fermentation and methods of making various chemical products.

Abstract: The present invention provides various combinations of genetic modifications to a transformed host cell that provide increase conversion of carbon to a chemical product. The present invention also provides methods of fermentation and methods of making various chemical products.

Abstract: Semiconductor device having on a single substrate (1) at least one memory cell (3) and at least one logic transistor (25); the at least one memory cell having a floating gate (5), a tunnel oxide layer (11) between the floating gate and the substrate (1), a control gate (15), and a control oxide layer (13) between the control gate (15) and the floating gate (5); the at least one logic transistor (25) having a logic transistor gate (5′, 15″) and a logic transistor gate oxide (11″) between the logic transistor gate (5′, 15″) and the substrate (1), the tunnel oxide layer (11) of the memory cell (3) and the logic transistor gate oxide (11″) having a same or substantially same predetermined first thickness. The invention also relates to a method of manufacturing such a device and to such a device that also comprises a high voltage transistor (17) which is optionally made so as to be an integral part of at least the memory cell (3).

Abstract: Semiconductor device having on a single substrate (1) at least one memory cell (3) and at least one logic transistor (25);

Abstract: In a stackable support for bracing plants or other items incapable of self support, an elongated primary member includes first and second ends. At least one retaining arm extends from the primary member adjacent to the second end and is adapted to engage and brace said plants or other supple items. Successive stackable supports are capable of being mounted one on top of the other to accommodate larger or growing plants, or other supple items.

Abstract: To assign upstream timeslots to network terminals (ANT1, ANT2, ANT3, ANT4) in a communication network wherein a common link (L) is shared in a time multiplexed way in the upstream direction from the network terminals (ANT1, ANT2, ANT3, ANT4) towards the main station (LIM), the main station (LIM) keeps track of at least one grant table (T1, T2) and at least one exceptional grant queue (Q1, Q2). The grant table (T1, T2) is scanned cyclically and the main station (LIM) downstream broadcasts a grant message for each entry of this grant table (T1, T2). This grant message assigns an upstream timeslot to the network terminal (ANT1) whose identifier (ID1) is memorized in the scanned table entry. If the scanned entry is empty, the main station (LIM) assigns an upstream timeslot to the network terminal (ANT2) whose identifier (ID2) is read from a non-empty exceptional grant queue (Q1, Q2).

Abstract: Semiconductor device having on a single substrate (1) at least one memory cell (3) and at least one logic transistor (25);