Abstract: A computer-implemented method for artificial intelligence (AI)-assisted mapping of electronic data interchange (EDI) data to an alternative format is provided. The method comprises receiving a message implementation guideline (MIG) specifying a first data format for an electronic document for use within an EDI environment and generating a map from the MIG, the map comprising mapping rules for transforming messages formatted according to the MIG to a second data format. Generating the map comprises identifying, from the MIG, rules text of interest; generating a prompt to a large language model (LLM), the prompt including the rules text and requesting that the large language model convert the rules text to respective mapping logic; inputting the prompt to the LLM; receiving the respective mapping logic from the LLM; and adding an AI-generated mapping rule to the map, the mapping rule comprising the respective mapping logic.

Abstract: A computer-implemented method for artificial intelligence (AI)-assisted mapping of electronic data interchange (EDI) data to an alternative format is provided. The method comprises receiving a message implementation guideline (MIG) specifying a first data format for an electronic document for use within an EDI environment and generating a map from the MIG, the map comprising mapping rules for transforming messages formatted according to the MIG to a second data format. Generating the map comprises identifying, from the MIG, rules text of interest; generating a prompt to a large language model (LLM), the prompt including the rules text and requesting that the large language model convert the rules text to respective mapping logic; inputting the prompt to the LLM; receiving the respective mapping logic from the LLM; and adding an AI-generated mapping rule to the map, the mapping rule comprising the respective mapping logic.

Abstract: Disclosed is a malodor control system that includes use of a malodor scavenger to sequester a malodor molecule to reduce and/or eliminate the noxious odor the malodor molecule generates. Some embodiments can include use of a substrate as a non-woven fabric sheet as a delivery system for the malodor scavenger. The substrate can include a polymer complexed with active ingredient to lock the active ingredient in place at a surface of the substrate via a binder so that the active ingredient is present at a predetermined activity level. After interacting with malodor molecules, at least some of the active ingredient migrates via passive diffusion to the substrate surface to maintain the predetermined activity level. Embodiments of the substrate are made from a blend of polyester and rayon, wherein rayon is made using viscose, allowing the substrate to be biodegradable and to handle an increased load of active ingredient.

Abstract: A technique relates probing a pass gate transistor in a static random access memory (SRAM) circuit. A gate probe is connected to a gate metal layer of the SRAM circuit, the gate metal layer being coupled to a gate of the pass gate transistor. A source probe is connected to a source metal layer of the SRAM circuit, the source metal layer being coupled to a source of the pass gate transistor. A drain probe is connected to a drain metal layer of the SRAM circuit, the drain metal layer being coupled to a drain of the pass gate transistor, the SRAM circuit comprising other transistors along with the pass gate transistor. The other transistors are free from connections for the probing so as not to cause the other transistors to have an unwanted effect on the pass gate transistor being probed.

Abstract: Formulations for promoting hair growth, preventing or mitigating hair loss, or enhancing skincare include a GHK peptide and a fullerene, such as C60, that has been processed to be safe for human consumption. In examples, the fullerene includes ESS60. In examples, the GHK peptide includes a GHK-Cu peptide, such as UTH29. Such therapeutic formulations may be applied to a person's skin or hair. In some embodiments, the peptide is dissolved in a polar solvent. In some embodiments, the fullerene is dissolved in a lipid solution. The formulations, when administered topically or introduced into the top layers of the epidermis, are effective in preventing or mitigating hair loss and graying that arises from age or elevated DHT levels. The formulations are also effective for use in the lightening of skin blemishes and prevention or mitigation of certain skin cancers that arise from age and UV damage.

Abstract: Systems and methods for providing a transportation marketplace are provided. A transportation server receives, from a client device of a user, a request for a transportation service. The transportation server determines a set of drivers in response to the request, the set of drivers further being available to provide the transportation service when the request is received. The transportation server provides the set of drivers to the client device, wherein each driver within the set of drivers is selectable by the user of the client device.

Abstract: A tempering composition for tempering grain in a tempering step and controlling pathogens susceptible to be present in and/or on said grain during the tempering step of the grain, said tempering step being eventually carried out before subjecting the tempered grain to a milling step; wherein said tempering composition comprises tempering-water and an oxidizing composition comprising at least one oxidizing agent and/or a precursor thereof, and eventually at least one an agriculturally acceptable excipient and/or at least one additive; and wherein the at least one oxidizing agent represents from 0.01 to 50% by weight of the oxidizing composition. A use and a method for tempering grain and controlling pathogens susceptible to be present on grain. An oxidizing composition for preparing the tempering composition. A use of the tempering composition for sanitizing mill systems. A method for sanitizing mill systems.

Abstract: First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.

Abstract: A technique relates probing a pass gate transistor in a static random access memory (SRAM) circuit. A gate probe is connected to a gate metal layer of the SRAM circuit, the gate metal layer being coupled to a gate of the pass gate transistor. A source probe is connected to a source metal layer of the SRAM circuit, the source metal layer being coupled to a source of the pass gate transistor. A drain probe is connected to a drain metal layer of the SRAM circuit, the drain metal layer being coupled to a drain of the pass gate transistor, the SRAM circuit comprising other transistors along with the pass gate transistor. The other transistors are free from connections for the probing so as not to cause the other transistors to have an unwanted effect on the pass gate transistor being probed.

Abstract: First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.

Abstract: A system and method to perform risk assessment or design rule determination for an integrated circuit involves generating two or more process variation contours based on corresponding two or more combinations of two or more factors that affect manufacturability of the integrated circuit. Each of the two or more process variation contours is associated with a probability. The method also includes generating a random number to select from among the two or more process variation contours based on a cumulative probability value associated with each of the two or more process variation contours. The cumulative probability values are determined from the probabilities. The risk assessment or the design rule determination is performed using selected ones of the two or more process variation contours. Fabrication yield is increased based on finalizing the physical layout using the process variation contours.

Abstract: A technique relates to a circuit. At least one 4 transistor (4T) static random access memory (SRAM) bitcell is included. Each of the 4T SRAM bitcells includes a first PFET, a first NFET, a second PFET, and a second NFET, the first PFET and the first NFET being coupled to form a first output node, and the second PFET and the second NFET being coupled to form a second output node. A pulldown circuit is coupled to the first NFET, the pulldown circuit operable to pull down a voltage at the first output node. A feedback circuit is operable to monitor the first output node, the feedback circuit operable to control the pulldown circuit.

Abstract: First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.

Abstract: A system and method to perform risk assessment or design rule determination for an integrated circuit involves generating two or more process variation contours based on corresponding two or more combinations of two or more factors that affect manufacturability of the integrated circuit. Each of the two or more process variation contours is associated with a probability. The method also includes generating a random number to select from among the two or more process variation contours based on a cumulative probability value associated with each of the two or more process variation contours. The cumulative probability values are determined from the probabilities. The risk assessment or the design rule determination is performed using selected ones of the two or more process variation contours. Fabrication yield is increased based on finalizing the physical layout using the process variation contours.

Abstract: Ultra dense and stable 4T SRAM designs are provided. In one aspect, a 4T SRAM bitcell includes: two NFETs cross-coupled with two PFETs, wherein the NFETs are both connected directly to a word line, wherein a first one of the PFETs is connected to a first bit line via a first one of the NFETs and a second one of the PFETs is connected to a second bit line via a second one of the NFETs, and wherein the PFETs are each separately connected to ground. An SRAM device including the present 4T SRAM bitcell as well as a method of operating the SRAM device are also provided.

Abstract: First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.

Abstract: Ultra dense and stable 4T SRAM designs are provided. In one aspect, a 4T SRAM bitcell includes: two NFETs cross-coupled with two PFETs, wherein the NFETs are both connected directly to a word line, wherein a first one of the PFETs is connected to a first bit line via a first one of the NFETs and a second one of the PFETs is connected to a second bit line via a second one of the NFETs, and wherein the PFETs are each separately connected to ground. An SRAM device including the present 4T SRAM bitcell as well as a method of operating the SRAM device are also provided.

Abstract: Systems and methods for providing discounts for shared transportation are described. A transportation server receives, from a client device of a first user, a first request for a shared transportation service. The transportation server receives, from a client device of a second user, a second request to join the shared transportation service. The transportation server calculates a first price for the first user for the shared transportation service based on at least a portion of a shared transportation service trip. The transportation server calculates a second price for the second user for the shared transportation service trip based on at least the portion of a shared transportation service trip.

Abstract: Systems and methods for providing a transportation marketplace are provided. A transportation server receives, from a client device of a user, a request for a transportation service. The transportation server determines a set of drivers in response to the request, the set of drivers further being available to provide the transportation service when the request is received. The transportation server provides the set of drivers to the client device, wherein each driver within the set of drivers is selectable by the user of the client device.