Abstract: Systems and methods for providing data security and selective communication are provided in which a classified communication is received and processed for retransmission to a recipient having a different clearance authorization than that associated with the communication. The retransmitted data includes a subset of data that is selected based on predetermined criteria, and is determined automatically by a guard application, such that the retransmitted information is properly sanitized.

Abstract: A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.

Abstract: A semiconductor structure is described. The structure includes a semiconductor substrate having a conductive gate abutting a gate insulator for controlling conduction of a channel region; and a source region and a drain region associated with the conductive gate, where the source region includes a first material and the drain region includes a second material, and where the conductive gate is self-aligned to the first material and the second material. In one embodiment, the first material includes Si and the second material includes SiGe. A method of forming a semiconductor structure is also described.

Abstract: An improved system and method of data partitioning for parallel processing of dynamically generated application data is provided. An application may send a request to partition the application data specified by a data partitioning policy and to process each of the data partitions according to processing instructions. The data partitioning policy may be flexibly defined by an application for partitioning data any number of ways, including balancing the data volume across each of the partitions or partitioning the data by data type. Asynchronous data partition processors may be instantiated to perform parallel processing of the partitioned data. The data may be partitioned according to the data partitioning policy and processed according to the processing instructions. And the results may be returned to the application.

Abstract: A toilet bowl refill water adjuster, including: a frame; a refill tube inlet and a refill tube outlet in the frame; a pair of opposing grooves in the frame, the opposing grooves having a series of positioning detents therein; and a roller moveable along in the pair of opposing grooves, wherein the frame is dimensioned to receive a toilet bowl refill tube passing through the refill tube inlet and outlet in the frame such that movement of the roller along in the pair of opposing grooves causes the roller to move in a direction to pinch the toilet bowl refill tube and thereby restrict flow through the toilet bowl refill tube, and wherein there is a linear relationship between the position of the roller in the pair of grooves and the flow rate through the toilet bowl refill tube.

Abstract: A static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array having a plurality of portions. The SRAM includes a plurality of voltage control circuits corresponding to respective ones of the plurality of portions of the array. Each of the plurality of voltage control circuits is coupled to an output of a power supply, each voltage control circuit having a function to temporarily reduce a voltage provided to power supply inputs of a plurality of SRAM cells that belong to a selected one of the plurality of portions of the SRAM. The power supply voltage to the selected portion is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected portion.

Abstract: A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.

Abstract: A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.

Abstract: The present invention relates to a semiconductor device comprising at least one static random access memory (SRAM) cell with self-aligned contacts. Specifically, the at least one SRAM cell comprises at least a first gate conductor that is located over a channel region between a source region and a drain region. The first gate conductor is covered by a dielectric cap comprising a protective dielectric material, and the source and drain regions are covered by non-protective dielectric material(s) that can be selectively removed against the protective material. In this manner, a self-aligned source or drain contact can be formed through the non-protective dielectric material(s) to contact either the source or the drain region, while the dielectric cap protects the first gate conductor during formation of the source or drain contact opening and thereby prevents shorting between the first gate conductor and the source or drain contact to be formed.

Abstract: A system and method for automatically adjusting one or more electrical parameters in a memory device, e.g., SRAM arrays. The system and method implements an SRAM sensing sub-array for accelerated collection of fail rate data for use in determining the operating point for optimum tradeoff between single event upset immunity and performance of a primary SRAM array. The accelerated fail rate data is input to an algorithm implemented for setting the SEU sensitivity of a primary SRAM memory array to a predetermined fail rate in an ionizing particle environment. The predetermined fail rate is maintained on a real-time basis in order to provide immunity to SEU consistent with optimum performance.

Abstract: The invention provides a method for determining the efficacy of a TNF? inhibitor, such as a TNF? antibody, or an antigen-binding portion thereof, for treating ankylosing spondylitis (AS), using a collagen degradation biomarker and/or a synovitis biomarker.

Abstract: A single stress liner is applied over different type semiconductor devices. The single stress liner avoids the problems of a dual/hybrid stress liner scheme by eliminating the meeting area. The single stress liner may be tensile or compressive. In one embodiment, the semiconductor device includes a static random access memory (SRAM) cell having numerous NFETs and PFETs. In this case, a compressive liner is placed over the SRAM cell, which is normally not ideal for the NFETs therein, but is desirable for the SRAM cell because continued miniaturization of the SRAMs typically requires slowing of the NFETs for the SRAM to maintain stabile. Where SRAM cells require increased speed, a single tensile stress liner can be implemented.

Abstract: A static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array. The array includes a plurality of rows and a plurality of columns. The SRAM includes a plurality of voltage control corresponding to respective ones of the plurality of columns of the array. Each of the plurality of voltage control circuits are coupled to an output of a power supply, each voltage control circuit having a function to temporarily reduce a voltage provided to power supply inputs of a plurality of SRAM cells that belong to a selected column of columns of the SRAM. The selected column is selected and the power supply voltage to that column is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected column.

Abstract: A reduction in the intersection of vias on the last layer (“VL”) and holes in the last thin metal layer (“MLHOLE”) can be achieved without degrading product yield or robustness or increasing copper dishing. The mutation of some dense redundant VLs to MLHOLEs decreases the number of intersections between VLs and MLHOLEs.

Abstract: A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.

Abstract: A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.

Abstract: A selective SOI structure having body contacts for all the devices while excluding the buried oxide that is directly underneath diffusions of DC nodes such as applied voltage Vdd, ground GND, reference voltage Vref, and other like DC nodes is provided. The selective SOI structure of the present invention can be used in ICs to enhance the performance of the circuit. The selective SOI structure of the present invention includes a silicon-on-insulator (SOI) substrate material comprising a top Si-containing layer having a plurality of SOI devices located thereon. The SOI devices are in contact with an underlying Si-containing substrate via a body contact region. A DC node diffusion region not containing an underlying buried oxide region is adjacent to one of the SOI devices.

Abstract: A reduction in the intersection of vias on the last layer (“VL”) and holes in the last thin metal layer (“MLHOLE”) can be achieved without degrading product yield or robustness or increasing copper dishing. The mutation of some dense redundant VLs to MLHOLEs decreases the number of intersections between VLs and MLHOLEs.

Abstract: Methods for designing a 6T SRAM cell having greater stability and/or a smaller cell size are provided. A 6T SRAM cell has a pair access transistors (NFETs), a pair of pull-up transistors (PFETs), and a pair of pull-down transistors (NFETs), wherein the access transistors have a higher threshold voltage than the pull-down transistors, which enables the SRAM cell to effectively maintain a logic “0” during access of the cell thereby increasing the stability of the cell, especially for cells during “half select.” Further, a channel width of a pull-down transistor can be reduced thereby decreasing the size of a high performance six transistor SRAM cell without effecting cell the stability during access. And, by decreasing the cell size, the overall design layout of a chip may also be decreased.

Abstract: An off-gimbal pointing system is improved using filtering of resolver and gyro responses respectively applied at the output of the resolvers and gyros for attenuating high frequencies resolver responses and gyro responses that effectively degrades the high frequency responses that are matched and above the control system bandwidth for improving the overall dynamic control of the off-gimbal pointing system for rejecting the affects of base motion disturbances and vibrations.