Patents by Inventor Roberto S. MAURINO
Roberto S. MAURINO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220239308Abstract: Devices and methods that aim to improve flicker noise rejection in switched-capacitor (SC) integrators are disclosed. An example SC integrator includes a first and a second sampling capacitors, an amplifier, an integrating capacitor, coupled at least to an output of the amplifier, and a switching arrangement. By adding (i.e., integrating in the integrating capacitor) sign-inverted samples of a flicker noise of the amplifier at every clock cycle of a master clock and by keeping the time distance/delay between those samples relatively small regardless of the master clock frequency, such a SC integrator may provide improvements in terms of rejecting the flicker noise of the amplifier.Type: ApplicationFiled: January 28, 2021Publication date: July 28, 2022Applicant: Analog Devices International Unlimited CompanyInventor: Roberto S. MAURINO
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Patent number: 10511316Abstract: A stage, suitable for use in and analog to digital converter or a digital to analog converter, comprises a plurality of slices. The slices can be operated together to form a composite output having reduced thermal noise, while each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This allows a fast conversion to be achieved without loss of noise performance. The slices can be sub-divided to reduce scaling mismatch between the most significant bit and the least significant bit. A shuffling scheme is implemented that allows shuffling to occur between the sub-sections of the slices without needing to implement a massively complex shuffler.Type: GrantFiled: August 2, 2018Date of Patent: December 17, 2019Assignee: ANALOG DEVICES GLOBAL UNLIMITED COMPANYInventors: Rares Bodnar, Roberto S. Maurino, Christopher Peter Hurrell, Asif Ahmad
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Publication number: 20190280704Abstract: A stage, suitable for use in and analog to digital converter or a digital to analog converter, comprises a plurality of slices. The slices can be operated together to form a composite output having reduced thermal noise, while each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This allows a fast conversion to be achieved without loss of noise performance. The slices can be sub-divided to reduce scaling mismatch between the most significant bit and the least significant bit. A shuffling scheme is implemented that allows shuffling to occur between the sub-sections of the slices without needing to implement a massively complex shuffler.Type: ApplicationFiled: August 2, 2018Publication date: September 12, 2019Applicant: Analog Devices Global Unlimited CompanyInventors: Rares BODNAR, Roberto S. MAURINO, Christopher Peter HURRELL, Asif AHMAD
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Patent number: 9391628Abstract: An input stage to an analog to digital converter (ADC) includes at least one sampling capacitor (SC) for sampling an input signal in acquire phases, a capacitive gain amplifier (CGA) for providing the input signal to the SC, and bandwidth control means. The bandwidth control means is configured to ensure that the SC has a first bandwidth during a first part of an acquire phase and has a second bandwidth during a subsequent, second, part of said acquire phase, the second bandwidth being smaller than the first. In this manner, first, the input signal is sampled at a higher, first, bandwidth allowing to take advantage of using a high-bandwidth CGA to minimize settling error on the SC, and, next, during a second part of the same acquire phase, the input signal is sampled at a lower, second, bandwidth advantageously decreasing noise resulting from the use of a high-bandwidth CGA.Type: GrantFiled: December 14, 2015Date of Patent: July 12, 2016Assignee: Analog Devices GlobalInventors: Colin G. Lyden, Pasquale Delizia, Sanjay Rajasekhar, Yogesh Jayarman Sharma, Arthur J. Kalb, Marvin L. Shu, Gerard Mora-Puchalt, Roberto S. Maurino
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Patent number: 9312825Abstract: An amplifier input stage comprising first and second p-type transistors, wherein sources of the first and second p-type transistors are connected to a first node, a drain of the first p-type transistor is connected to a first output of the amplifier input stage, a drain of the second p-type transistor is connected to a second output of the amplifier input stage, a gate of the first p-type transistor is configured to receive a first signal of an input stage differential input signal and a gate of the second p-type transistor is configured to receive a second signal of the input stage differential input signal; first and second n-type transistors, wherein sources of the first and second n-type transistors are connected to a second node, a drain of the first n-type transistor is connected to a third output of the amplifier input stage, a drain of the second n-type transistor is connected to a fourth output of the amplifier input stage, a gate of the first n-type transistor is configured to receive the first signType: GrantFiled: May 9, 2014Date of Patent: April 12, 2016Assignee: Analog Devices GlobalInventor: Roberto S. Maurino
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Patent number: 9294037Abstract: Apparatus and methods for autozero amplifiers are provided herein. In certain configurations, an autozero amplifier includes at least three transconductance stages and an autozero timing control circuit configured to control an autozero sequence of the transconductance stages. The autozero timing control circuit can stagger autozeroing of the transconductance stages, such that a relatively small amount of the amplifier's amplification circuitry is connected to or disconnected from the amplifier's signal path at any given time. For example, in certain configurations, when one of the transconductance stages in autozeroed over a particular time interval, the remaining transconductance stages can operate in parallel to provide amplification during that time interval.Type: GrantFiled: March 24, 2014Date of Patent: March 22, 2016Assignee: Analog Devices GlobalInventors: Roberto S. Maurino, Venkata Aruna Srikanth Nittala, Abhilasha Kawle, Sanjay Rajasekhar
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Publication number: 20150326193Abstract: An amplifier input stage comprising first and second p-type transistors, wherein sources of the first and second p-type transistors are connected to a first node, a drain of the first p-type transistor is connected to a first output of the amplifier input stage, a drain of the second p-type transistor is connected to a second output of the amplifier input stage, a gate of the first p-type transistor is configured to receive a first signal of an input stage differential input signal and a gate of the second p-type transistor is configured to receive a second signal of the input stage differential input signal; first and second n-type transistors, wherein sources of the first and second n-type transistors are connected to a second node, a drain of the first n-type transistor is connected to a third output of the amplifier input stage, a drain of the second n-type transistor is connected to a fourth output of the amplifier input stage, a gate of the first n-type transistor is configured to receive the first signType: ApplicationFiled: May 9, 2014Publication date: November 12, 2015Inventor: Roberto S. Maurino
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Publication number: 20150270805Abstract: Apparatus and methods for autozero amplifiers are provided herein. In certain configurations, an autozero amplifier includes at least three transconductance stages and an autozero timing control circuit configured to control an autozero sequence of the transconductance stages. The autozero timing control circuit can stagger autozeroing of the transconductance stages, such that a relatively small amount of the amplifier's amplification circuitry is connected to or disconnected from the amplifier's signal path at any given time. For example, in certain configurations, when one of the transconductance stages in autozeroed over a particular time interval, the remaining transconductance stages can operate in parallel to provide amplification during that time interval.Type: ApplicationFiled: March 24, 2014Publication date: September 24, 2015Applicant: Analog Devices TechnologyInventors: Roberto S. Maurino, Venkata Aruna Srikanth Nittala, Abhilasha Kawle, Sanjay Rajasekhar
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Patent number: 9124290Abstract: An integrator system may have a pair of sampling circuits each having a sampling capacitor to sample a respective component of a differential input signal, and an integrator having inputs coupled to outputs of the sampling circuits. The system may have a shorting switch coupled between input terminals of the sampling capacitors. The shorting switch may be engaged during an interstitial phase between sampling and output phases of the sampling circuits. By shorting input terminals of the sampling capacitors together, the design reduces current drawn by the system and, in some designs, severs relationships between current draw and information content sampled by the system. The integrator system may receive analog and digital input signals.Type: GrantFiled: February 1, 2013Date of Patent: September 1, 2015Assignee: ANALOG DEVICES GLOBALInventors: Adrian W. Sherry, Gabriel Banarie, Roberto S. Maurino
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Patent number: 9065477Abstract: A digital-to-analog (DAC) element may include a plurality of switches arranged to form two circuit branches between a current source and a first and a second outputs. The first circuit branch may include two switches defining parallel current paths between the current source and the first output terminal. The second circuit branch may include two switches defining parallel current paths between the current source and the second output terminal. A control circuit, responsive to an input signal that selects one of the circuit branches, may provide control signals to close one of switches in the selected circuit branch in a first portion of a clock cycle and to close the other of the switches in the selected circuit branch in a second portion of the clock cycle.Type: GrantFiled: February 12, 2014Date of Patent: June 23, 2015Assignee: ANALOG DEVICES GLOBALInventors: Sanjay Rajasekhar, Abhilasha Kawle, Roberto S Maurino, Srikanth Nittala
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Publication number: 20150061908Abstract: A digital-to-analog (DAC) element may include a plurality of switches arranged to form two circuit branches between a current source and a first and a second outputs. The first circuit branch may include two switches defining parallel current paths between the current source and the first output terminal. The second circuit branch may include two switches defining parallel current paths between the current source and the second output terminal. A control circuit, responsive to an input signal that selects one of the circuit branches, may provide control signals to close one of switches in the selected circuit branch in a first portion of a clock cycle and to close the other of the switches in the selected circuit branch in a second portion of the clock cycle.Type: ApplicationFiled: February 12, 2014Publication date: March 5, 2015Applicant: ANALOG DEVICES TECHNOLOGYInventors: Sanjay RAJASEKHAR, Abhilasha KAWLE, Roberto S. MAURINO, Srikanth NITTALA
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Patent number: 8791754Abstract: A programmable gain amplifier (“PGA”) may include a differential amplifier, a pair of input capacitors, a pair of feedback capacitors provided in feedback configuration about the amplifier, a first chop circuit, provided at an input of the PGA and an output of the PGA and a second chop circuit provided at an output of the PGA. The PGA also may include circuit systems to sample voltages across the input capacitors in a sampling phase. The sampled voltages may correspond to a difference between a common mode voltage of input signals to the PGA and a common mode voltage of the differential amplifier. The sampled voltage, thus, defines a common mode voltage at the amplifier's inputs during other phases of operation, when the chop circuits are operational.Type: GrantFiled: August 22, 2012Date of Patent: July 29, 2014Assignee: Analog Devices, Inc.Inventors: Colin G. Lyden, Roberto S. Maurino, Damien J. McCartney
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Publication number: 20140203957Abstract: A continuous time input stage including a first digital-to-analog converter (DAC) including a first DAC code input, a second DAC including a second DAC code input, a first set of switches coupled to the output of the first DAC, a second set of switches coupled to the output of the second DAC, and an amplifier configured to receive the output of either the first DAC or the second DAC.Type: ApplicationFiled: January 22, 2013Publication date: July 24, 2014Applicant: Analog Devices TechnologyInventors: Roberto S. MAURINO, Sanjay RAJASEKHAR, Abhilasha KAWLE
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Patent number: 8779958Abstract: A continuous time input stage including a first digital-to-analog converter (DAC) including a first DAC code input, a second DAC including a second DAC code input, a first set of switches coupled to the output of the first DAC, a second set of switches coupled to the output of the second DAC, and an amplifier configured to receive the output of either the first DAC or the second DAC.Type: GrantFiled: January 22, 2013Date of Patent: July 15, 2014Assignee: Analog Devices TechnologyInventors: Roberto S. Maurino, Sanjay Rajasekhar, Abhilasha Kawle
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Patent number: 8766836Abstract: A sigma delta modulator may include a loop filter and an adder configured to accept an output of the loop filter and a dither input signal. The adder may be further configured to combine the output of the loop filter and the dither input signal into a combined output signal. The sigma delta modulator may further include a quantizer configured to accept the combined output signal from the adder, and quantize the combined signal into a quantizer output signal. The sigma delta modulator may further include a first subtractor configured to accept the quantizer output signal and subtract the dither input signal from the quantizer output signal.Type: GrantFiled: December 14, 2012Date of Patent: July 1, 2014Assignee: Analog Devices, Inc.Inventors: Roberto S. Maurino, Colin G. Lyden
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Publication number: 20130293294Abstract: A programmable gain amplifier (“PGA”) may include a differential amplifier, a pair of input capacitors, a pair of feedback capacitors provided in feedback configuration about the amplifier, a first chop circuit, provided at an input of the PGA and an output of the PGA and a second chop circuit provided at an output of the PGA. The PGA also may include circuit systems to sample voltages across the input capacitors in a sampling phase. The sampled voltages may correspond to a difference between a common mode voltage of input signals to the PGA and a common mode voltage of the differential amplifier. The sampled voltage, thus, defines a common mode voltage at the amplifier's inputs during other phases of operation, when the chop circuits are operational.Type: ApplicationFiled: August 22, 2012Publication date: November 7, 2013Applicant: ANALOG DEVICES, INC.Inventors: Colin G. LYDEN, Roberto S. MAURINO, Damien J. MCCARTNEY
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Publication number: 20130207820Abstract: A sigma delta modulator may include a loop filter and an adder configured to accept an output of the loop filter and a dither input signal. The adder may be further configured to combine the output of the loop filter and the dither input signal into a combined output signal. The sigma delta modulator may further include a quantizer configured to accept the combined output signal from the adder, and quantize the combined signal into a quantizer output signal. The sigma delta modulator may further include a first subtractor configured to accept the quantizer output signal and subtract the dither input signal from the quantizer output signal.Type: ApplicationFiled: December 14, 2012Publication date: August 15, 2013Inventors: Roberto S. MAURINO, Colin G. LYDEN
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Publication number: 20130207821Abstract: An integrator system may have a pair of sampling circuits each having a sampling capacitor to sample a respective component of a differential input signal, and an integrator having inputs coupled to outputs of the sampling circuits. The system may have a shorting switch coupled between input terminals of the sampling capacitors. The shorting switch may be engaged during an interstitial phase between sampling and output phases of the sampling circuits. By shorting input terminals of the sampling capacitors together, the design reduces current drawn by the system and, in some designs, severs relationships between current draw and information content sampled by the system. Configurations are disclosed for analog and digital input signals.Type: ApplicationFiled: February 1, 2013Publication date: August 15, 2013Applicant: Analog Devices TechnologyInventors: Adrian W. SHERRY, Gabriel BANARIE, Roberto S. MAURINO