Patents by Inventor Roberto Tiziani
Roberto Tiziani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230411258Abstract: A semiconductor device comprises at least one semiconductor die electrically coupled to a set of electrically conductive leads, and package molding material molded over the at least one semiconductor die and the electrically conductive leads. At least a portion of the electrically conductive leads is exposed at a rear surface of the package molding material to provide electrically conductive pads. The electrically conductive pads comprise enlarged end portions extending at least partially over the package molding material and configured for coupling to a printed circuit board.Type: ApplicationFiled: September 1, 2023Publication date: December 21, 2023Applicant: STMicroelectronics S.r.l.Inventors: Michele DERAI, Roberto TIZIANI
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Patent number: 11749588Abstract: A semiconductor device comprises at least one semiconductor die electrically coupled to a set of electrically conductive leads, and package molding material molded over the at least one semiconductor die and the electrically conductive leads. At least a portion of the electrically conductive leads is exposed at a rear surface of the package molding material to provide electrically conductive pads. The electrically conductive pads comprise enlarged end portions extending at least partially over the package molding material and configured for coupling to a printed circuit board.Type: GrantFiled: December 14, 2020Date of Patent: September 5, 2023Assignee: STMicroelectronics S.r.l.Inventors: Michele Derai, Roberto Tiziani
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Publication number: 20230230948Abstract: A method comprises molding laser direct structuring material onto at least one semiconductor die, forming resist material on the laser direct structuring material, producing mutually aligned patterns of electrically-conductive formations in the laser direct structuring material and etched-out portions of the resist material having lateral walls sidewise of said electrically-conductive formations via laser beam energy, and forming electrically-conductive material at said etched-out portions of the resist material, the electrically-conductive material having lateral confinement surfaces at said lateral walls of said etched-out portions of the resist material.Type: ApplicationFiled: March 28, 2023Publication date: July 20, 2023Applicant: STMICROELECTRONICS S.r.l.Inventors: Roberto TIZIANI, Guendalina CATALANO
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Publication number: 20230135498Abstract: Embodiments of the present disclosure relate to a semiconductor package, a method of forming the package and an electronic device. For example, the semiconductor package may comprise a first substrate assembly comprising a first surface and a second surface opposite the first surface. The semiconductor package may also comprise one or more chips connected or coupled to the first surface of the first substrate assembly by a first thermally and electrically conductive connecting material. In addition, the semiconductor package further comprises a second substrate assembly comprising a third surface and a fourth surface opposite the third surface, the third surface and the first surface being arranged to face each other, and the third surface being connected to one or more chips by a second thermally and electrically conductive connecting material. At least one of the first surface and the third surface is shaped to have a stepped pattern to match a surface of the one or more chips.Type: ApplicationFiled: October 27, 2022Publication date: May 4, 2023Applicants: STMICROELECTRONICS S.r.l., SHENZHEN STS MICROELECTRONICS CO., LTD.Inventors: Yi Ming LIANG, Roberto TIZIANI, Qian LIU, Feng DING
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Patent number: 11626379Abstract: A method comprises molding laser direct structuring material onto at least one semiconductor die, forming resist material on the laser direct structuring material, producing mutually aligned patterns of electrically-conductive formations in the laser direct structuring material and etched-out portions of the resist material having lateral walls sidewise of said electrically-conductive formations via laser beam energy, and forming electrically-conductive material at said etched-out portions of the resist material, the electrically-conductive material having lateral confinement surfaces at said lateral walls of said etched-out portions of the resist material.Type: GrantFiled: March 11, 2021Date of Patent: April 11, 2023Assignee: STMICROELECTRONICS S.r.l.Inventors: Roberto Tiziani, Guendalina Catalano
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Publication number: 20230031356Abstract: A pre-molded leadframe includes a laminar structure having empty spaces therein and a first thickness with a die pad having opposed first and second die pad surfaces. Insulating pre-mold material is molded onto the laminar structure. The pre-mold material penetrates the empty spaces and provides a laminar pre-molded substrate having the first thickness with the first die pad surface left exposed. The die pad has a second thickness that is less than the first thickness. One or more pillar formations are provided protruding from the second die pad surface to a height equal to a difference between the first and second thicknesses. With the laminar structure clamped between surfaces of a mold, the first die pad surface and pillar formations abut against the mold surfaces. The die pad is thus effectively clamped between the clamping surfaces countering undesired flashing of the pre-mold material over the first die pad surface.Type: ApplicationFiled: July 26, 2022Publication date: February 2, 2023Applicant: STMicroelectronics S.r.l.Inventors: Mauro MAZZOLA, Roberto TIZIANI
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Patent number: 11557547Abstract: A leadframe for semiconductor devices, the leadframe comprising a die pad portion having a first planar die-mounting surface and a second planar surface opposed the first surface, the first surface and the second surface having facing peripheral rims jointly defining a peripheral outline of the die pad wherein the die pad comprises at least one package molding compound receiving cavity opening at the periphery of said first planar surface.Type: GrantFiled: December 18, 2020Date of Patent: January 17, 2023Assignee: STMicroelectronics S.r.l.Inventors: Roberto Tiziani, Mauro Mazzola
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Publication number: 20220384209Abstract: Semiconductor chips are arranged on an elongated substrate and encapsulated by an insulating encapsulation. Electrically conductive formations and electrically conductive plating lines are plated on the insulating encapsulation using, for example, Laser Direct Structuring (LDS) or Direct Copper Interconnect (DCI) material. The electrically conductive plating lines include first transverse plating lines as well as second plating lines branching out from the first plating lines towards the electrically conductive formations. A first partial cutting step is then performed to form grooves which remove the first plating lines. An insulating material is dispensed in the grooves to encapsulate the end portions of the second plating lines. A second cutting step median along the groove and through the elongate substrate is performed to produce singulated semiconductor devices (such as “die pad up” Quad-Flat No-lead (QFN) packages). End portions of the second plating lines are encapsulated by the insulating material.Type: ApplicationFiled: May 25, 2022Publication date: December 1, 2022Applicant: STMicroelectronics S.r.l.Inventors: Roberto TIZIANI, Antonio BELLIZZI
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Publication number: 20220352057Abstract: A substrate includes electrically-conductive tracks. A semiconductor chip is arranged on the substrate and electrically coupled to selected ones of the electrically-conductive tracks. Containment structures are provided at selected locations on the electrically-conductive tracks, where the containment structures have respective perimeter walls defining respective cavities. Each cavity is configured to accommodate a base portion of a pin holder. These pin holders are soldered to the electrically-conductive tracks within the cavities defined by the containment structures. Each containment structure may be formed by a ring of resist material configured to receive solder and maintain the pin holders in a desired alignment position.Type: ApplicationFiled: April 26, 2022Publication date: November 3, 2022Applicants: STMicroelectronics S.r.l., STMicroelectronics Pte LtdInventors: Roberto TIZIANI, Laurent HERARD
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Publication number: 20220214430Abstract: An electronic module for generating light pulses includes an electronic card or interposer, a LASER-diode lighting module, and a LASER-diode driver module. The interposer has an edge recess in which the lighting module is completely inserted. The driver module is arranged on top of the interposer and the lighting module. The electrical connections for driving the LASER diodes are obtained without resorting to wire bonding in order to reduce the parasitic inductances.Type: ApplicationFiled: January 4, 2022Publication date: July 7, 2022Applicants: STMicroelectronics S.r.l., STMicroelectronics (Rousset) SAS, STMicroelectronics Application GmbHInventors: Romeo LETOR, Roberto TIZIANI, Alfio RUSSO, Antoine PAVLIN, Nadia LECCI, Manuel GAERTNER
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Publication number: 20220199500Abstract: A leadframe includes a pattern of electrically-conductive formations with one or more sacrificial connection formations extending bridge-like between a pair of electrically-conductive formations. The sacrificial connection formation or formations are formed at one of the first surface and the second surface of the leadframe and have a thickness less than the leadframe thickness between the first surface and the second surface. A filling of electrically-insulating material is molded between the electrically-conductive formations of the leadframe, with electrically-insulating material molded between the connection formation(s) and the other surface of the leadframe. The sacrificial connection formation(s) counter deformation and displacement of parts during formation and pre-molding of the leadframe.Type: ApplicationFiled: December 14, 2021Publication date: June 23, 2022Applicant: STMicroelectronics S.r.l.Inventors: Mauro MAZZOLA, Roberto TIZIANI
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Publication number: 20220102258Abstract: A packaged semiconductor device includes a substrate having a first surface and a second surface opposite the first surface. At least one semiconductor die is mounted at the first surface of the substrate. Electrically-conductive leads are arranged around the substrate, and electrically-conductive formations couple the at least one semiconductor die to selected leads of the electrically-conductive leads. A package molding material is molded onto the at least one semiconductor die, onto the electrically-conductive leads and onto the electrically-conductive formations. The package molding material leaves the second surface of the substrate uncovered by the package molding material. The substrate is formed by a layer of electrically-insulating material.Type: ApplicationFiled: September 28, 2021Publication date: March 31, 2022Applicant: STMicroelectronics S.r.l.Inventor: Roberto TIZIANI
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Publication number: 20210305191Abstract: A method comprises molding laser direct structuring material onto at least one semiconductor die, forming resist material on the laser direct structuring material, producing mutually aligned patterns of electrically-conductive formations in the laser direct structuring material and etched-out portions of the resist material having lateral walls sidewise of said electrically-conductive formations via laser beam energy, and forming electrically-conductive material at said etched-out portions of the resist material, the electrically-conductive material having lateral confinement surfaces at said lateral walls of said etched-out portions of the resist material.Type: ApplicationFiled: March 11, 2021Publication date: September 30, 2021Applicant: STMICROELECTRONICS S.r.l.Inventors: Roberto TIZIANI, Guendalina CATALANO
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Publication number: 20210193591Abstract: A leadframe for semiconductor devices, the leadframe comprising a die pad portion having a first planar die-mounting surface and a second planar surface opposed the first surface, the first surface and the second surface having facing peripheral rims jointly defining a peripheral outline of the die pad wherein the die pad comprises at least one package molding compound receiving cavity opening at the periphery of said first planar surface.Type: ApplicationFiled: December 18, 2020Publication date: June 24, 2021Applicant: STMicroelectronics S.r.l.Inventors: Roberto TIZIANI, Mauro MAZZOLA
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Publication number: 20210183752Abstract: A semiconductor device comprises at least one semiconductor die electrically coupled to a set of electrically conductive leads, and package molding material molded over the at least one semiconductor die and the electrically conductive leads. At least a portion of the electrically conductive leads is exposed at a rear surface of the package molding material to provide electrically conductive pads. The electrically conductive pads comprise enlarged end portions extending at least partially over the package molding material and configured for coupling to a printed circuit board.Type: ApplicationFiled: December 14, 2020Publication date: June 17, 2021Applicant: STMicroelectronics S.r.l.Inventors: Michele DERAI, Roberto TIZIANI
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Publication number: 20170125998Abstract: It is described an electronic device 1 comprising a temperature detection component 2 and an integrated electronic power component 3, the device being adapted to be mounted on the substrate S. The electronic integrated power component 3 has a first surface portion 31, adapted to be mounted on the substrate S, and a second surface portion 32, opposite to the first surface portion. The temperature detection component 2 comprises two sensor terminals 21, 22, adapted to be connected to the substrate S by means of wire bonding W, and further comprises a temperature sensor 20, configured to detect a temperature T representative of the temperature T3 of the integrated electronic power component 3 and to provide, by means of the two sensor terminals 21, 22, an electrical signal V representative of the detected temperature T.Type: ApplicationFiled: October 27, 2016Publication date: May 4, 2017Inventors: Roberto TIZIANI, Fabrizio SOGLIO, Giovanni Franco GIULIANI
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Publication number: 20160105997Abstract: A liquid cooling system for an electronic component, comprising an exchanger plate having a first wall suitable to be at least partially interfaced to an electronic component to be cooled and a second wall, placed in contact with a cooling liquid, a plurality of heat sink elements, associated to said second wall and influenced by the cooling fluid so as to dissipate heat, wherein the heat sink elements are shaped according to regular patterns that extend parallel to a main extension direction and that comprise a plurality of loops, wherein each loop comprises a continuous curvilinear section that extends cantilevered from a first to a second attachment end fixed to the second wall. Advantageously, the continuous curvilinear section is shaped so that, a first and a second plane being traced perpendicular to the second wall passing respectively through said first and second ends, the continuous curvilinear section extends at least partially outside the space defined between said perpendicular planes.Type: ApplicationFiled: October 13, 2015Publication date: April 14, 2016Inventors: Roberto TIZIANI, Enrico TAGLIAFERRI
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Patent number: 7803663Abstract: A method is provided for manufacturing a fully moulded Multi Media Card package obtained by laser cutting wherein at least some edges and the corners around the package have rounded profile and a sufficient smoothness for a safe handling. The method includes providing a rounded groove on a substrate back side of the package, all around the package profile, and cutting the edges of said package by a laser cutting line passing through said groove. This new technique allows the use of all the 24.0 mm width of the MMC package for the substrate 2, thus increasing the surface available for electronic components.Type: GrantFiled: August 31, 2005Date of Patent: September 28, 2010Assignee: STMicroelectronics, S.r.l.Inventors: Roberto Tiziani, Giovanni Frezza
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Patent number: 7459387Abstract: A semiconductor electronic device includes a die of semiconductor material and a support. The die of semiconductor material includes an integrated electronic circuit and a plurality of contact pads associated with the electronic circuit and connected electrically to the support by wire leads. Each contact pad may include a lower layer of aluminum, copper, or alloys thereof, and an upper layer including at least one film of a metal and/or metallic alloy including nickel, palladium, or alloys thereof, and being deposited by an electroless chemical process.Type: GrantFiled: September 23, 2004Date of Patent: December 2, 2008Assignee: STMicroelectronics S.r.L.Inventors: Roberto Tiziani, Carlo Passagrilli
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Publication number: 20060057823Abstract: A method is provided for manufacturing a fully moulded Multi Media Card package obtained by laser cutting wherein at least some edges and the corners around the package have rounded profile and a sufficient smoothness for a safe handling. The method includes providing a rounded groove on a substrate back side of the package, all around the package profile, and cutting the edges of said package by a laser cutting line passing through said groove. This new technique allows the use of all the 24.0 mm width of the MMC package for the substrate 2, thus increasing the surface available for electronic components.Type: ApplicationFiled: August 31, 2005Publication date: March 16, 2006Inventors: Roberto Tiziani, Giovanni Frezza