SEMICONDUCTOR DEVICE AND CORRESPONDING METHOD

Abstract

A semiconductor device comprises at least one semiconductor die electrically coupled to a set of electrically conductive leads, and package molding material molded over the at least one semiconductor die and the electrically conductive leads. At least a portion of the electrically conductive leads is exposed at a rear surface of the package molding material to provide electrically conductive pads. The electrically conductive pads comprise enlarged end portions extending at least partially over the package molding material and configured for coupling to a printed circuit board.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No. 17/120,996, filed Dec. 14, 2020, now U.S. Pat. No. 11,749,588, which claims the priority benefit of Italian Application for Patent No. 102019000024259, filed on Dec. 17, 2019, the contents of which are hereby incorporated by reference in their entireties to the maximum extent allowable by law.

TECHNICAL FIELD

The description relates to manufacturing semiconductor devices.

One or more embodiments may be applied to manufacturing integrated circuits (ICs).

BACKGROUND

Semiconductor devices such as integrated circuits may be provided with packages of various types. For instance, quad-flat no-leads (QFN) packages and land grid array (LGA) packages are examples of surface-mount technology (SMT) packages known in the art.

QFN packages are near chip-scale plastic encapsulated packages provided with a planar leadframe substrate, wherein perimeter lands on the package rear (e.g., bottom) side are configured to provide electrical connections to a printed circuit board (PCB). The leads of the leadframe are thus fully incorporated in the package molding compound. QFN packages may include an exposed thermal pad to improve heat transfer out of the integrated circuit, into the printed circuit board.

LGA packages also have leads fully incorporated in the package molding compound, and comprise a (rectangular) grid of contacts on the bottom side of the package. The contacts on the package are configured to be coupled to a grid of contacts on the PCB.

Both QFN and LGA packages (as well as other SMT packages) do not have external leads, but rather have “lands” or “pads” that are directly couplable to the PCB pads for soldering by means of solder paste or solder alloy. The mounting (soldering) step may be complex and may result in a wide variability of welding strength and structure. Additionally, the different coefficients of thermal expansion between the package and the printed circuit board may lead to high stress in the solder material and/or to high thermal fatigue of QFN/LGA packages once mounted on a printed circuit board.

In this context, the use of “wettable flanks” is known in the art. Wettable flanks help increase wettability of the leads with the purpose of improving solder adhesion and overall welding strength by increasing the solder attachment area on the vertical side of the lands or pads. Wettable flanks may only slightly improve the solder joint reliability, and facilitate automatic optical inspection of the solder joint after the surface mounting process, for surface mount process control.

Packaged semiconductor devices providing improved solder joint reliability and/or stronger anchorage to the PCB are desirable.

There is a need in the art to contribute in providing packaged semiconductor devices, e.g., comprising a QFN- or LGA-type package, with improved solder joint reliability and/or stronger anchorage to the printed circuit board.

SUMMARY

One or more embodiments may relate to a semiconductor device (e.g., an integrated circuit).

One or more embodiments may relate to a corresponding method of manufacturing semiconductor devices.

One or more embodiments may provide a packaged semiconductor device (e.g., comprising a QFN or LGA package) comprising at least one semiconductor die electrically coupled to a set of electrically conductive leads, and package molding material molded over the at least one semiconductor die and the electrically conductive leads. At least a portion of the electrically conductive leads may be exposed at a rear surface of the package molding material to provide electrically conductive pads. The electrically conductive pads may comprise enlarged end portions extending at least partially over the package molding material and configured for coupling to a printed circuit board.

BRIEF DESCRIPTION OF THE DRAWINGS

One or more embodiments will now be described, by way of example only, with reference to the annexed figures, wherein:

FIG. 1 is a perspective view exemplary of a semiconductor device comprising a QFN package, shown upside-down (i.e., with the rear side facing upwards);

FIG. 2 is a view of the rear side of the semiconductor device of FIG. 1;

FIG. 3A is a magnified view of a portion of the rear side of the semiconductor device of FIG. 2;

FIG. 3B is a side view of the portion of the semiconductor device of FIG. 3A mounted on a printed circuit board;

FIG. 4A is a magnified view of a portion of the rear side of a semiconductor device according to embodiments;

FIG. 4B is a side view of the portion of the semiconductor device of FIG. 4A mounted on a printed circuit board; and

FIGS. 5A to 5G are exemplary of steps of a method of manufacturing semiconductor devices according to embodiments.

DETAILED DESCRIPTION

In the ensuing description, one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured.

Reference to “an embodiment” or “one embodiment” in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment” or “in one embodiment” that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

Throughout the figures annexed herein, like parts or elements are indicated with like references/numerals and a corresponding description will not be repeated for brevity.

The references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.

By way of introduction to the detailed description of exemplary embodiments, reference may be first had to FIGS. 1 and 2, which are exemplary of a semiconductor device 10 comprising a QFN package.

While reference is made mainly to QFN packages in the present description and drawings for the sake of conciseness, one or more embodiments may be applied to other types of “leadless” packages, e.g., LGA packages.

As current in the art, together with other elements/features not visible in the Figures, a semiconductor device 10 as exemplified herein may comprise package molding material 100 encapsulating a semiconductor die (not visible in FIGS. 1 and 2), the molding material 100 being shaped to provide a rear (e.g., bottom) side 10A of the semiconductor device 10 configured for electrical and mechanical coupling to a printed circuit board.

A set of electrically conductive “lands” or “pads” 12 may be provided on the rear (or bottom) side 10A, e.g., at the periphery thereof, as illustrated in FIGS. 1 and 2. Additionally or alternatively, the pads 12 may be arranged over the entire area of the rear side 10A, as customary in LGA packages. The pads 12 may be electrically coupled to the semiconductor die encapsulated in the molding material 100.

Optionally, the package may include an exposed thermal pad 14 on the rear side 10A. The thermal pad 14 may be thermally coupled to the semiconductor die encapsulated in the molding material 100 to improve heat transfer out of the integrated circuit 10.

Overall, the electrical pads 12 and the thermal pad 14 may provide the leadframe of the integrated circuit 10.

The (minimum) spacing between two adjacent pads 12 may be constrained by manufacturing constraints of the leadframe. Typically, the corresponding solder pads on a PCB may be wider and/or less spaced. For instance, FIG. 2 shows a bottom view of an exemplary integrated circuit 10 having electrical pads 12 and a thermal pad 14 (illustrated with solid lines), and a corresponding exemplary arrangement of solder pads 12′ and 14′ as may be present on a printed circuit board configured for coupling to the integrated circuit 10.

FIG. 3A is a magnified view exemplary of a portion of the rear side 10A of the integrated circuit 10, e.g., portion 20 illustrated in FIG. 2. FIG. 3B is a corresponding side view of portion 20, exemplary of the integrated circuit 10 mounted on a printed circuit board by means of soldering material 32 interposed between the electrical pads 12 of the integrated circuit 10 and the respective solder pads 12′ on the PCB 30.

It is noted that, as a consequence of the spacing D_o between pads 12 being (considerably) larger than the spacing d between pads 12′, electro-mechanical coupling of the integrated circuit to the PCB 30 may turn out to be unsatisfactory.

In one or more embodiments as exemplified in FIGS. 4A and 4B, reliability of such electro-mechanical coupling may be improved by increasing the area of the electrical pads 12 of the integrated circuit 10.

FIG. 4A is a magnified view exemplary of a portion 20 of the rear side 10A of an integrated circuit 10 according to one or more embodiments. FIG. 4B is a corresponding side view of portion 20, exemplary of the integrated circuit 10 mounted on a printed circuit board by means of soldering material 42.

As exemplified herein, a metallic layer may be selectively provided at the pads 12 after molding of the package material 100 to provide enlarged end portions 44 of the pads. The enlarged end portions 44 may thus partially extend over the molding material 100 at the interface between the pads 12 and the molding material 100 (e.g., “sidewise” of the body portion 12 of the pads which are embedded in the molding material), thereby increasing the area of the pads suitable for electrical and/or mechanical coupling to the soldering pads 12′.

Therefore, in one or more embodiments, a (thick) “pedestal” of metal material may be grown over the surface of the pads 12 and/or 14 left exposed by the molding material 100, thereby providing larger pads (i.e., providing a reduced spacing D_n between pads 12, which increase the soldering surface) and an increase of the standoff between the semiconductor package 100 and the printed circuit board 30. As a result, solder joint reliability may be improved and/or a stronger anchorage of the integrated circuit to the PCB may be obtained.

In one or more embodiments, the enlarged end portions 44 may be provided (e.g., grown) over the pads 12 and/or 14 after molding of the package material 100 by means of galvanic plating.

Providing the enlarged end portions 44 by galvanic plating may be advantageous insofar as it may facilitate growing the metal 44 (sidewise) over the molding compound 100 at the interface between the pads 12 and/or 14 and the molding compound 100, i.e., it may facilitate properly increasing the area of the pads (as exemplified in FIG. 4B).

Additionally or alternatively, any other selective metal deposition technique that would result in an isotropic growth of metal at the pads 12 and/or 14 may be used to form the enlarged portions 44.

In one or more embodiments, the thickness of the enlarged end portions 44 may be in the range of 10 μm to 100 μm, preferably 50 μm to 70 μm.

In one or more embodiments, the enlarged end portions 44 may extend (sidewise) over the molding compound 100 from the interface between the respective body portion of pad 12 and/or 14 and the molding compound 100 (see length D_p in FIG. 4B) for about 10 μm to 100 μm, preferably 50 μm to 70 μm.

In one or more embodiments, the enlarged end portions 44 may comprise at least one metal selected out of copper (Cu), nickel (Ni), palladium (Pd) and gold (Au). Preferably, the enlarged end portions 44 comprise copper (Cu).

In one or more embodiments, a further metallic layer may be provided over the enlarged end portions 44. For instance, the further metallic layer may comprise tin (Sn) plated over the enlarged end portions 44 at the pads 12 and/or 14.

One or more embodiments may provide improved reliability (e.g., longer life on board) over previous solutions, e.g., over solutions involving wettable flanks.

FIGS. 5A to 5G are exemplary of possible steps of a method of manufacturing semiconductor devices according to one or more embodiments. In FIGS. 5A-5G, manufacturing of a pair of semiconductor devices in exemplified.

As exemplified in FIG. 5A, an otherwise conventional leadframe may be provided as a first manufacturing step. For each semiconductor device, the leadframe may comprise a die pad 14 and respective leads 12.

As exemplified in FIG. 5B, at least one semiconductor die 50 may be mounted on each die pad 14 of the leadframe. For instance, the semiconductor dies 50 may be attached on the die pads 14 via die attach material 52, e.g., soft-solder die attach material and/or glue.

As exemplified in FIG. 5C, wire bonding may be carried out to provide electrical coupling between a semiconductor die 50 and the respective leads 12 via bonding wires 54.

As exemplified in FIG. 5D, package molding material 100 may be molded to encapsulate the semiconductor dies 50 and the leadframe, leaving exposed the electrical pads 12 and the thermal pads 14 at the rear side of the semiconductor devices.

As exemplified in FIG. 5E, a metallic layer 44 may be provided at the pads 12 and/or 14 after molding of the package material 100, thereby providing metallic “bumps” (the enlarged end portions) at the package leads. The enlarged end portions 44 may be grown, for instance, by galvanic plating. The thickness (t) of the enlarged end portions 44 may be in the range of 10 μm to 100 μm, preferably 50 μm to 70 μm. The lateral extension (D_p) of the enlarged end portions 44 may be in the range of 10 μm to 100 μm, preferably 50 μm to 70 μm. The enlarged end portions 44 may comprise one or more metals selected out of copper (Cu), nickel (Ni), palladium (Pd) and gold (Au).

As exemplified in FIG. 5F, a further metallic layer 56 may be provided over the metallic layer 44, e.g., by plating. The further metallic layer 56 may comprise tin (Sn).

As exemplified in FIG. 5G, the manufacturing method may comprise singulating the semiconductor devices 10, e.g., by cutting or sawing along sawing lines, as conventional in the art.

As exemplified herein, a semiconductor device (e.g., 10) may comprise: at least one semiconductor die (e.g., 50) electrically coupled (e.g., 54) to a set of electrically conductive leads; and package molding material (e.g., 100) molded over the at least one semiconductor die and the electrically conductive leads, wherein at least a portion of the electrically conductive leads is exposed at a rear surface (e.g., 10A) of the package molding material to provide electrically conductive pads (e.g., 12, 44).

As exemplified herein, the electrically conductive pads may comprise enlarged end portions (e.g., 44) extending at least partially over the package molding material, the enlarged end portions configured for coupling to a printed circuit board (e.g., 30).

As exemplified herein, the electrically conductive pads may comprise body portions (e.g., stem portions or web portions 12) embedded in the package molding material and the enlarged end portions may protrude from the package molding material.

As exemplified herein, the enlarged end portions may extend over the package molding material sidewise of said body portions for a length (e.g., D_p) of 10 μm to 100 μm, preferably 50 μm to 70 μm.

As exemplified herein, the enlarged end portions may comprise galvanic plating grown material.

As exemplified herein, the enlarged end portions may comprise at least one metal selected out of copper, nickel, palladium and gold, preferably copper.

As exemplified herein, a thickness (e.g., t) of the enlarged end portions may be in the range of 10 μm to 100 μm, preferably 50 μm to 70 μm.

As exemplified herein, a semiconductor device may comprise a metallic layer (e.g., 56) plated over the enlarged end portions. The metallic layer may comprise tin.

As exemplified herein, a semiconductor device may comprise a thermally conductive pad (e.g., 14). The thermally conductive pad may comprise a respective enlarged end portion extending at least partially over the package molding material and configured for coupling to a printed circuit board.

As exemplified herein, a semiconductor device may comprise a quad-flat no-lead package or a land grid array package.

As exemplified herein, a method may comprise: providing a leadframe comprising at least one die pad and at least one respective set of electrically conductive leads; mounting at least one semiconductor die onto the at least one die pad; electrically coupling the at least one semiconductor die to electrically conductive leads in the respective at least one set of electrically conductive leads; molding package molding material onto the at least one semiconductor die and the leadframe, the package molding material exposing at least a portion of the electrically conductive leads at a rear surface of the package molding material to provide electrically conductive pads; and providing enlarged end portions of the electrically conductive pads extending at least partially over the package molding material, the enlarged end portions configured for coupling to a printed circuit board.

Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the extent of protection.

The claims are an integral part of the technical teaching provided herein in respect of the embodiments.

The extent of protection is defined by the annexed claims.

Claims

1. A semiconductor device, comprising:

a leadframe including a set of electrically conductive leads;

a semiconductor die electrically coupled to said set of electrically conductive leads; and

package molding material molded over the semiconductor die and the electrically conductive leads of the leadframe, wherein at least a portion of the electrically conductive leads is not covered by the package molding material;

electrically conductive pads at said portion of the electrically conductive leads which are not covered by the package molding material;

a plating layer on the electrically conductive pads that forms first enlarged end portions wherein said plating layer extends at least partially over a rear surface of the package molding material;

wherein the first enlarged end portions are configured for coupling to a printed circuit board.

2. The semiconductor device of claim 1, wherein the electrically conductive leads comprise body portions embedded in the package molding material and said plating layer forming the first enlarged end portions protrudes from the body portions at the rear surface of the package molding material.

3. The semiconductor device of claim 2, wherein the plating layer forming the first enlarged end portions extends over the rear surface of the package molding material sidewise of said body portions for a length of 10 μm to 100 μm.

4. The semiconductor device of claim 2, wherein the plating layer forming the first enlarged end portions extend over the rear surface of the package molding material sidewise of said body portions for a length of 50 μm to 70 μm.

5. The semiconductor device of claim 1, wherein said plating layer forming the first enlarged end portions comprises copper.

6. The semiconductor device of claim 1, wherein said plating layer forming the first enlarged end portions comprises at least one metal selected from the group consisting of: nickel, palladium and gold.

7. The semiconductor device of claim 1, wherein a thickness of the plating layer forming said first enlarged end portions is in a range of 10 μm to 100 μm.

8. The semiconductor device of claim 1, wherein a thickness of the plating layer forming said first enlarged end portions is in a range of 50 μm to 70 μm.

9. The semiconductor device of claim 1, further comprising a metallic layer plated over the plating layer forming said first enlarged end portions.

10. The semiconductor device of claim 9, wherein the metallic layer comprises tin.

11. The semiconductor device of claim 1, wherein said leadframe further comprises a thermally conductor to which the semiconductor die is mounted, wherein at least a portion of the thermally conductor that is not covered by the package molding material provides a thermally conductive pad; and wherein said plating layer is also present on the thermally conductive pad to form a second enlarged end portion extending at least partially over the rear surface of the package molding material.

12. The semiconductor device of claim 1, configured as a quad-flat no-lead package.

13. The semiconductor device of claim 1, configured as a land grid array package.

14. A semiconductor device, comprising:

a semiconductor die mounted to a thermally conductive pad and electrically coupled to a set of electrically conductive leads;

package molding material molded over the semiconductor die, the thermally conductive pad and the electrically conductive leads, wherein at least a portion of the thermally conductive pad is exposed at a rear surface of the package molding material; and

a plating layer on the thermally conductive pad forming an enlarged portion extending at least partially over the rear surface of the package molding material, wherein the enlarged portion is configured for coupling to a printed circuit board.

15. The semiconductor device of claim 14, wherein the thermally conductive pad comprises a body portion embedded in the package molding material and the plating layer forming said enlarged end portion protrudes from the rear surface of the package molding material.

16. The semiconductor device of claim 15, wherein the plating layer forming said enlarged end portion extends over the rear surface of the package molding material sidewise of said body portions for a length of 10 μm to 100 μm.

17. The semiconductor device of claim 15, wherein the plating layer forming said enlarged end portion extends over the rear surface of the package molding material sidewise of said body portions for a length of 50 μm to 70 μm.

18. The semiconductor device of claim 15, wherein the plating layer forming said enlarged end portion comprises at least one metal selected from the group consisting of: copper, nickel, palladium and gold.

19. The semiconductor device of claim 14, wherein a thickness of plating layer forming said enlarged end portion is in a range of 10 μm to 100 μm.

20. The semiconductor device of claim 14, wherein a thickness of the plating layer forming said enlarged end portion is in a range of 50 μm to 70 μm.

21. The semiconductor device of claim 14, further comprising a metallic layer plated over the plating layer forming said enlarged end portion.

22. The semiconductor device of claim 21, wherein the metallic layer comprises tin.