Patents by Inventor Robin Hsin-Kuo Chao
Robin Hsin-Kuo Chao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190252493Abstract: A method of fabricating a semiconductor device includes forming a fin in a substrate and depositing a spacer material on the fin. The method includes recessing the spacer material so that a surface of the fin is exposed. The method includes removing a portion of the fin within lateral sidewalls of the spacer material to form a recess, leaving a portion of the fin on the lateral sidewalls. The method further includes depositing a semiconductor material within the recess.Type: ApplicationFiled: April 18, 2019Publication date: August 15, 2019Inventors: ROBIN HSIN KUO CHAO, KANGGUO CHENG, NICOLAS LOUBET
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Publication number: 20190252520Abstract: A semiconductor device includes a first nanosheet stack, a second nanosheet stack, and a third nanosheet stack arranged on a substrate. The semiconductor device includes a gate arranged on the first nanosheet stack, the second nanosheet stack, and the third nanosheet stack. The semiconductor device includes a channel extending through the gate and from the first nanosheet stack, the second nanosheet stack, and to the third nanosheet stack in a serpentine fashion. The semiconductor device includes a first source/drain and a second source/drain arranged on opposing sides of the gate.Type: ApplicationFiled: April 23, 2019Publication date: August 15, 2019Inventors: ROBIN HSIN KUO CHAO, CHOONGHYUN LEE, HENG WU, CHUN WING YEUNG, JINGYUN Zhang
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Patent number: 10374034Abstract: A method for manufacturing a semiconductor device includes forming a first nanosheet device and forming a second nanosheet device spaced apart from the first nanosheet device in respective first and second regions corresponding to first and second types. The first and second nanosheet devices respectively include a first and a second plurality of work function metal layers, and a work function metal layer extends from the first and second plurality of work function metal layers in the space between the nanosheet devices. In the method, part of the work function metal layer is removed from the space between the nanosheet devices, and the removed part of the work function metal layer is replaced with a polymer brush layer. The first plurality of work function metal layers is selectively removed from the first region with respect to the polymer brush layer.Type: GrantFiled: May 21, 2018Date of Patent: August 6, 2019Assignee: International Business Machines CorporationInventors: Chi-Chun Liu, Muthumanickam Sankarapandian, Kristin Schmidt, Ekmini Anuja De Silva, Noel Arellano, Robin Hsin Kuo Chao, Chun Wing Yeung, Zhenxing Bi
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Publication number: 20190237562Abstract: Techniques for VFET gate length control are provided. In one aspect, a method of forming a VFET device includes: patterning fins in a substrate; forming first polymer spacers alongside opposite sidewalls of the fins; forming second polymer spacers offset from the fins by the first polymer spacers; removing the first polymer spacers selective to the second polymer spacers; reflowing the second polymer spacers to close a gap to the fins; forming a cladding layer above the second polymer spacers; removing the second polymer spacers; forming gates along opposite sidewalls of the fins exposed in between the bottom spacers and the cladding layer, wherein the gates have a gate length Lg set by removal of the second polymer spacers; forming top spacers above the cladding layer; and forming top source and drains above the top spacers. A VFET device is also provided.Type: ApplicationFiled: February 1, 2018Publication date: August 1, 2019Inventors: Chi-Chun Liu, Chun Wing Yeung, Robin Hsin Kuo Chao, Zhenxing Bi, Kristin Schmidt, Yann Mignot
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Patent number: 10355103Abstract: A semiconductor device includes a first nanosheet stack, a second nanosheet stack, and a third nanosheet stack arranged on a substrate. The semiconductor device includes a gate arranged on the first nanosheet stack, the second nanosheet stack, and the third nanosheet stack. The semiconductor device includes a channel extending through the gate and from the first nanosheet stack, the second nanosheet stack, and to the third nanosheet stack in a serpentine fashion. The semiconductor device includes a first source/drain and a second source/drain arranged on opposing sides of the gate.Type: GrantFiled: December 18, 2017Date of Patent: July 16, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robin Hsin Kuo Chao, Choonghyun Lee, Heng Wu, Chun Wing Yeung, Jingyun Zhang
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Patent number: 10340341Abstract: A method of fabricating a semiconductor device includes forming a fin in a substrate and depositing a spacer material on the fin. The method includes recessing the spacer material so that a surface of the fin is exposed. The method includes removing a portion of the fin within lateral sidewalls of the spacer material to form a recess, leaving a portion of the fin on the lateral sidewalls. The method further includes depositing a semiconductor material within the recess.Type: GrantFiled: December 20, 2017Date of Patent: July 2, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robin Hsin Kuo Chao, Kangguo Cheng, Nicolas Loubet
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Publication number: 20190189748Abstract: A method includes forming a gate on a first fin, a second fin, and a third fin arranged on a substrate. The method includes depositing a semiconductor material on the first fin, the second fin, and the third fin. The method further includes depositing an interlayer dielectric (ILD) on the first fin, the second fin, and the third fin. The method further includes forming a first trench and a second trench through the ILD on a first side of the gate, and a third trench and a fourth trench through the ILD on a second side of the gate, the second trench coupling the second fin to the third fin, and the third trench coupling the first fin to the second fin. The method includes depositing a metal in the first trench, the second trench, the third trench, and the fourth trench.Type: ApplicationFiled: December 18, 2017Publication date: June 20, 2019Inventors: ROBIN HSIN KUO CHAO, CHOONGHYUN LEE, HENG WU, CHUN WING YEUNG, JINGYUN Zhang
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Publication number: 20190189740Abstract: A method of fabricating a semiconductor device includes forming a fin in a substrate and depositing a spacer material on the fin. The method includes recessing the spacer material so that a surface of the fin is exposed. The method includes removing a portion of the fin within lateral sidewalls of the spacer material to form a recess, leaving a portion of the fin on the lateral sidewalls. The method further includes depositing a semiconductor material within the recess.Type: ApplicationFiled: December 20, 2017Publication date: June 20, 2019Inventors: ROBIN HSIN KUO CHAO, KANGGUO CHENG, NICOLAS LOUBET
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Publication number: 20190189776Abstract: A semiconductor device includes a first nanosheet stack, a second nanosheet stack, and a third nanosheet stack arranged on a substrate. The semiconductor device includes a gate arranged on the first nanosheet stack, the second nanosheet stack, and the third nanosheet stack. The semiconductor device includes a channel extending through the gate and from the first nanosheet stack, the second nanosheet stack, and to the third nanosheet stack in a serpentine fashion. The semiconductor device includes a first source/drain and a second source/drain arranged on opposing sides of the gate.Type: ApplicationFiled: December 18, 2017Publication date: June 20, 2019Inventors: ROBIN HSIN KUO CHAO, CHOONGHYUN LEE, HENG WU, CHUN WING YEUNG, JINGYUN Zhang
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Patent number: 10312326Abstract: A method includes forming a gate on a first fin, a second fin, and a third fin arranged on a substrate. The method includes depositing a semiconductor material on the first fin, the second fin, and the third fin. The method further includes depositing an interlayer dielectric (ILD) on the first fin, the second fin, and the third fin. The method further includes forming a first trench and a second trench through the ILD on a first side of the gate, and a third trench and a fourth trench through the ILD on a second side of the gate, the second trench coupling the second fin to the third fin, and the third trench coupling the first fin to the second fin. The method includes depositing a metal in the first trench, the second trench, the third trench, and the fourth trench.Type: GrantFiled: December 18, 2017Date of Patent: June 4, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robin Hsin Kuo Chao, Choonghyun Lee, Heng Wu, Chun Wing Yeung, Jingyun Zhang
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Patent number: 10276695Abstract: A method for manufacturing a semiconductor device includes forming a stacked configuration of first and second semiconductor layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a second semiconductor layer stacked on a first semiconductor layer, forming a plurality of dummy gates spaced apart from each other on the stacked configuration, wherein the plurality of dummy gates cover a portion of the stacked configuration in a channel region, performing an implantation of a semiconductor material on exposed portions of the stacked configuration in a source/drain region, wherein the implantation increases a concentration of the semiconductor material in the exposed portions of the stacked configuration, and selectively removing first semiconductor layers having an increased concentration of the semiconductor material from the source/drain region, wherein the removed first semiconductor layers correspond in position to the first semiconductor layers in the chaType: GrantFiled: July 20, 2017Date of Patent: April 30, 2019Assignee: International Business Machines CorporationInventors: Robin Hsin-Kuo Chao, Michael A. Guillorn, Chi-Chun Liu, Shogo Mochizuki, Chun W. Yeung
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Publication number: 20190109040Abstract: A semiconductor device is fabricated with a first layer of a first sacrificial material deposited over a surface of a substrate. A first set of layers of a second sacrificial material and a second set of layers of a channel material are deposited over the first layer. A liner is deposited in a first recess, which exposes a first connection end of a layer in the second set, where the first recess reaches into the substrate for at least a fraction of a total depth of the substrate. An insulator material is filled in the first recess and etched up to a stop depth, stopping the etching at a height above the surface of the substrate. The liner is removed from at least the first connection end of the layer in the second set. An electrical connection is formed with a source/drain structure using the first connection end.Type: ApplicationFiled: October 9, 2017Publication date: April 11, 2019Applicant: International Business Machines CorporationInventors: ROBIN HSIN KUO CHAO, Kangguo Cheng, Nicolas Loubet, Pietro Montanini, Ruilong Xie
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Publication number: 20180047835Abstract: A method for manufacturing a semiconductor device includes forming a stacked configuration of first and second semiconductor layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a second semiconductor layer stacked on a first semiconductor layer, forming a plurality of dummy gates spaced apart from each other on the stacked configuration, wherein the plurality of dummy gates cover a portion of the stacked configuration in a channel region, performing an implantation of a semiconductor material on exposed portions of the stacked configuration in a source/drain region, wherein the implantation increases a concentration of the semiconductor material in the exposed portions of the stacked configuration, and selectively removing first semiconductor layers having an increased concentration of the semiconductor material from the source/drain region, wherein the removed first semiconductor layers correspond in position to the first semiconductor layers in the chaType: ApplicationFiled: July 20, 2017Publication date: February 15, 2018Inventors: Robin Hsin-Kuo Chao, Michael A. Guillorn, Chi-Chun Liu, Shogo Mochizuki, Chun W. Yeung
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Publication number: 20180047834Abstract: A method for manufacturing a semiconductor device includes forming a stacked configuration of first and second semiconductor layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a second semiconductor layer stacked on a first semiconductor layer, forming a plurality of dummy gates spaced apart from each other on the stacked configuration, wherein the plurality of dummy gates cover a portion of the stacked configuration in a channel region, performing an implantation of a semiconductor material on exposed portions of the stacked configuration in a source/drain region, wherein the implantation increases a concentration of the semiconductor material in the exposed portions of the stacked configuration, and selectively removing first semiconductor layers having an increased concentration of the semiconductor material from the source/drain region, wherein the removed first semiconductor layers correspond in position to the first semiconductor layers in the chaType: ApplicationFiled: July 20, 2017Publication date: February 15, 2018Inventors: Robin Hsin-Kuo Chao, Michael A. Guillorn, Chi-Chun Liu, Shogo Mochizuki, Chun W. Yeung
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Patent number: 9831324Abstract: A method for manufacturing a semiconductor device includes forming a stacked configuration of first and second semiconductor layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a second semiconductor layer stacked on a first semiconductor layer, forming a plurality of dummy gates spaced apart from each other on the stacked configuration, wherein the plurality of dummy gates cover a portion of the stacked configuration in a channel region, performing an implantation of a semiconductor material on exposed portions of the stacked configuration in a source/drain region, wherein the implantation increases a concentration of the semiconductor material in the exposed portions of the stacked configuration, and selectively removing first semiconductor layers having an increased concentration of the semiconductor material from the source/drain region, wherein the removed first semiconductor layers correspond in position to the first semiconductor layers in the chaType: GrantFiled: August 12, 2016Date of Patent: November 28, 2017Assignee: International Business Machines CorporationInventors: Robin Hsin-Kuo Chao, Michael A. Guillorn, Chi-Chun Liu, Shogo Mochizuki, Chun W. Yeung
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Publication number: 20150134286Abstract: Embodiments of the present invention provide an improved method and system for assessing non-uniformity of features in the measurement area (within the beam spot) on a semiconductor structure, (e.g. wafer), such as a non-uniform film thickness. The scattering from non-uniform features is modeled. Post-processing the residual of theoretical and collected spectra is performed to assess a measure of non-uniformity from within an incident spot beam of a spectrum acquisition tool.Type: ApplicationFiled: November 12, 2013Publication date: May 14, 2015Applicant: International Business Machines CorporationInventors: Robin Hsin-Kuo Chao, Yunlin Zhang