Patents by Inventor Roden R. Topacio

Roden R. Topacio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10403589
    Abstract: Various semiconductor workpiece polymer layers and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a polymer layer to a passivation structure of a semiconductor workpiece where the semiconductor workpiece has first and second semiconductor chips separated by a dicing street. A first opening is patterned in the polymer layer with opposing edges pulled back from the dicing street. A mask is applied over the first opening. A first portion of the passivation structure is etched while using the polymer layer as an etch mask.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: September 3, 2019
    Assignee: ATI Technologies ULC
    Inventor: Roden R. Topacio
  • Publication number: 20170301638
    Abstract: Various semiconductor workpiece polymer layers and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a polymer layer to a passivation structure of a semiconductor workpiece where the semiconductor workpiece has first and second semiconductor chips separated by a dicing street. A first opening is patterned in the polymer layer with opposing edges pulled back from the dicing street. A mask is applied over the first opening. A first portion of the passivation structure is etched while using the polymer layer as an etch mask.
    Type: Application
    Filed: June 30, 2017
    Publication date: October 19, 2017
    Inventor: Roden R. Topacio
  • Patent number: 9728518
    Abstract: Various semiconductor workpiece polymer layers and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a polymer layer to a passivation structure of a semiconductor workpiece where the semiconductor workpiece has first and second semiconductor chips separated by a dicing street. A first opening is patterned in the polymer layer with opposing edges pulled back from the dicing street. A mask is applied over the first opening. A first portion of the passivation structure is etched while using the polymer layer as an etch mask.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: August 8, 2017
    Assignee: ATI Technologies ULC
    Inventor: Roden R. Topacio
  • Publication number: 20170110428
    Abstract: Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes forming a first underbump metallization layer on a semiconductor chip is provided. The first underbump metallization layer has a hub, a first portion extending laterally from the hub, and a spoke connecting the hub to the first portion. A polymer layer is applied to the first underbump metallization layer. The polymer layer includes a first opening in alignment with the hub and a second opening in alignment with the spoke. A portion of the spoke is removed via the second opening to sever the connection between the hub and the first portion.
    Type: Application
    Filed: December 30, 2016
    Publication date: April 20, 2017
    Inventors: Roden R. Topacio, Suming Hu, Yip Seng Low
  • Patent number: 9576923
    Abstract: Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes forming a first underbump metallization layer on a semiconductor chip is provided. The first underbump metallization layer has a hub, a first portion extending laterally from the hub, and a spoke connecting the hub to the first portion. A polymer layer is applied to the first underbump metallization layer. The polymer layer includes a first opening in alignment with the hub and a second opening in alignment with the spoke. A portion of the spoke is removed via the second opening to sever the connection between the hub and the first portion.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: February 21, 2017
    Assignee: ATI Technologies ULC
    Inventors: Roden R. Topacio, Suming Hu, Yip Seng Low
  • Patent number: 9318457
    Abstract: Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes depositing a layer of a first metallic material on a semiconductor chip. The first layer has a first physical quantity. A layer of a second metallic material is deposited on the layer of the first metallic material. The second layer has a second physical quantity. The first and second layers are reflowed to form a solder structure with a desired ratio of the first metallic material to the second metallic material.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: April 19, 2016
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Roden R. Topacio, Neil McLellan
  • Publication number: 20150340334
    Abstract: Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes depositing a layer of a first metallic material on a semiconductor chip. The first layer has a first physical quantity. A layer of a second metallic material is deposited on the layer of the first metallic material. The second layer has a second physical quantity. The first and second layers are reflowed to form a solder structure with a desired ratio of the first metallic material to the second metallic material.
    Type: Application
    Filed: August 5, 2015
    Publication date: November 26, 2015
    Inventors: Roden R. Topacio, Neil McLellan
  • Publication number: 20150279794
    Abstract: Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes forming a first underbump metallization layer on a semiconductor chip is provided. The first underbump metallization layer has a hub, a first portion extending laterally from the hub, and a spoke connecting the hub to the first portion. A polymer layer is applied to the first underbump metallization layer. The polymer layer includes a first opening in alignment with the hub and a second opening in alignment with the spoke. A portion of the spoke is removed via the second opening to sever the connection between the hub and the first portion.
    Type: Application
    Filed: April 1, 2014
    Publication date: October 1, 2015
    Inventors: Roden R. Topacio, Suming Hu, Yip Seng Low
  • Publication number: 20150279728
    Abstract: Various semiconductor workpiece polymer layers and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a polymer layer to a passivation structure of a semiconductor workpiece where the semiconductor workpiece has first and second semiconductor chips separated by a dicing street. A first opening is patterned in the polymer layer with opposing edges pulled back from the dicing street. A mask is applied over the first opening. A first portion of the passivation structure is etched while using the polymer layer as an etch mask.
    Type: Application
    Filed: April 1, 2014
    Publication date: October 1, 2015
    Inventor: Roden R. Topacio
  • Patent number: 9142520
    Abstract: Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes depositing a layer of a first metallic material on a semiconductor chip. The first layer has a first physical quantity. A layer of a second metallic material is deposited on the layer of the first metallic material. The second layer has a second physical quantity. The first and second layers are reflowed to form a solder structure with a desired ratio of the first metallic material to the second metallic material.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: September 22, 2015
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Roden R. Topacio, Neil McLellan
  • Patent number: 8847383
    Abstract: An integrated circuit package strip employs a stiffener layer that houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: September 30, 2014
    Assignee: ATI Technologies ULC
    Inventors: Neil R. McLellan, Vincent K. Chan, Roden R. Topacio, III
  • Patent number: 8772083
    Abstract: Various substrates or circuit boards for receiving a semiconductor chip and methods of processing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in a solder mask positioned on a side of a substrate. The first opening does not extend to the side. A second opening is formed in the solder mask that extends to the side. The first opening may serve as an underfill anchor site.
    Type: Grant
    Filed: September 10, 2011
    Date of Patent: July 8, 2014
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Andrew K W Leung, Roden R. Topacio, Yu-Ling Hsieh, Yip Seng Low
  • Patent number: 8647974
    Abstract: Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip that has a first conductor pad and a passivation structure. A second conductor pad is fabricated around but not in physical contact with the first conductor pad to leave a gap. The second conductor pad is adapted to protect a portion of the passivation structure.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: February 11, 2014
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Roden R. Topacio, Michael Z. Su, Neil McLellan
  • Patent number: 8637983
    Abstract: An integrated circuit (IC) product includes a redistribution layer (RDL) having at least one conductive layer configured to distribute electrical information from one location to another location in the IC. The RDL also includes a plurality of wire bond pads and a plurality of solder pads. The plurality of solder pads each includes a solder wettable material that is in direct electrical communication with the RDL.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: January 28, 2014
    Assignee: ATI Technologies ULC
    Inventors: Liane Martinez, Roden R. Topacio, Yip Seng Low
  • Publication number: 20130256871
    Abstract: Methods and apparatus to inhibit cracks and delaminations in a semiconductor chip solder bump and to reduce pad parasitic capacitance are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first insulating layer over plural conductor pads of a semiconductor chip and forming an opening over each of the conductor pads. An individual solder structure is coupled to the insulating layer. The solder structure has a projection in each of the openings and in electrical contact with one of the plural conductor pads.
    Type: Application
    Filed: March 29, 2012
    Publication date: October 3, 2013
    Inventors: Roden R. Topacio, Neil McLellan
  • Publication number: 20130147026
    Abstract: According an embodiment, a package-on-package heatsink interposer for use between a top package and a bottom package of a package-on-package device, may include a top heatsink below the top package; an interposer substrate below the top heatsink; a bottom heatsink below the interposer substrate; a first interposer substrate metal layer between the interposer substrate and the top heatsink; a second interposer substrate metal layer between the interposer substrate and the bottom heatsink; and interposer solder balls between the second interposer substrate metal layer and the bottom package.
    Type: Application
    Filed: December 12, 2011
    Publication date: June 13, 2013
    Applicant: ATI Technologies ULC
    Inventors: Roden R. TOPACIO, Liane Martinez, Yip Seng Low
  • Publication number: 20130113084
    Abstract: Various semiconductor substrates and methods of processing the same are disclosed. In one aspect, a method of manufacturing is provided that includes mounting a first semiconductor chip on a side of a first substrate. The first substrate has at least one thru-silicon-via. An insulating layer is molded on the side of the first substrate. The insulating layer provides a support structure to enable handling of the first substrate.
    Type: Application
    Filed: November 4, 2011
    Publication date: May 9, 2013
    Inventors: Roden R. Topacio, Neil McLellan, Yip Seng Low, Jianguo Li
  • Publication number: 20130062786
    Abstract: Various substrates or circuit boards for receiving a semiconductor chip and methods of processing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in a solder mask positioned on a side of a substrate. The first opening does not extend to the side. A second opening is formed in the solder mask that extends to the side. The first opening may serve as an underfill anchor site.
    Type: Application
    Filed: September 10, 2011
    Publication date: March 14, 2013
    Inventors: Andrew KW Leung, Roden R. Topacio, Yu-Ling Hsieh, Yip Seng Low
  • Patent number: 8389340
    Abstract: Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in an insulating layer applied to a side of a semiconductor chip. The first opening does not extend through to the side. A second opening is formed in the insulating layer that exposes a portion of the side.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: March 5, 2013
    Assignee: ATI Technologies ULC
    Inventors: Roden R. Topacio, Neil McLellan
  • Publication number: 20130049190
    Abstract: Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes depositing a layer of a first metallic material on a semiconductor chip. The first layer has a first physical quantity. A layer of a second metallic material is deposited on the layer of the first metallic material. The second layer has a second physical quantity. The first and second layers are reflowed to form a solder structure with a desired ratio of the first metallic material to the second metallic material.
    Type: Application
    Filed: August 30, 2011
    Publication date: February 28, 2013
    Inventors: Roden R. Topacio, Neil McLellan