Abstract: A method and apparatus for depositing a tantalum nitride barrier layer is provided for use in an integrated processing tool. The tantalum nitride is deposited by atomic layer deposition. The tantalum nitride is removed from the bottom of features in dielectric layers to reveal the conductive material under the deposited tantalum nitride. Optionally, a tantalum layer may be deposited by physical vapor deposition after the tantalum nitride deposition. Optionally, the tantalum nitride deposition and the tantalum deposition may occur in the same processing chamber.

Abstract: A method and apparatus for depositing a tantalum nitride barrier layer is provided for use in an integrated processing tool. The tantalum nitride is deposited by atomic layer deposition. The tantalum nitride is removed from the bottom of features in dielectric layers to reveal the conductive material under the deposited tantalum nitride. Optionally, a tantalum layer may be deposited by physical vapor deposition after the tantalum nitride deposition. Optionally, the tantalum nitride deposition and the tantalum deposition may occur in the same processing chamber.

Abstract: A method and apparatus for depositing a tantalum nitride barrier layer is provided for use in an integrated processing tool. The tantalum nitride is deposited by atomic layer deposition. The tantalum nitride is removed from the bottom of features in dielectric layers to reveal the conductive material under the deposited tantalum nitride. Optionally, a tantalum layer may be deposited by physical vapor deposition after the tantalum nitride deposition. Optionally, the tantalum nitride deposition and the tantalum deposition may occur in the same processing chamber.

Abstract: The present invention generally provides a precleaning process prior to metallization for submicron features on substrates. The method includes cleaning the submicron features with radicals from a plasma of a reactive gas such as oxygen, a mixture of CF4/O2, or a mixture of He/NF3, wherein the plasma is preferably generated by a remote plasma source and the radicals are delivered to a chamber in which the substrate is disposed. Native oxides remaining in the submicron features are preferably reduced in a second step by treatment with radicals from a plasma containing hydrogen. Following the first or both precleaning steps, the features can be filled with metal by available metallization techniques which typically include depositing a barrier/liner layer on exposed dielectric surfaces prior to deposition of aluminum, copper, or tungsten. The precleaning and metallization steps can be conducted on available integrated processing platforms.

Abstract: The present invention generally provides a precleaning process prior to metallization for submicron features on substrates. The method includes cleaning the submicron features with radicals from a plasma of a reactive gas such as oxygen, a mixture of CF4/O2, or a mixture of He/NF3, wherein the plasma is preferably generated by a remote plasma source and the radicals are delivered to a chamber in which the substrate is disposed. Native oxides remaining in the submicron features are preferably reduced in a second step by treatment with radicals from a plasma containing hydrogen. Following the first or both precleaning steps, the features can be filled with metal by available metallization techniques which typically include depositing a barrier/liner layer on exposed dielectric surfaces prior to deposition of aluminum, copper, or tungsten. The precleaning and metallization steps can be conducted on available integrated processing platforms.

Abstract: The present invention relates generally to an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD metal layer is substantially void-free.

Abstract: The present invention relates generally to an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD metal layer is substantially void-free.

Abstract: The present invention generally provides a precleaning process prior to moralization for submicron features on substrates. The method includes cleaning the submicron features with radicals from a plasma of a reactive gas such as oxygen, a mixture of CF4/O2, or a mixture of He/NF3, wherein the plasma is preferably generated by a remote plasma source and the radicals are delivered to a chamber in which the substrate is disposed. Native oxides remaining in the submicron features are preferably reduced in a second step by treatment with radicals from a plasma containing hydrogen. Following the first or both precleaning steps, the features can be filled with metal by available moralization techniques which typically include depositing a barrier/liner layer on exposed dielectric surfaces prior to deposition of aluminum, copper, or tungsten. The precleaning and moralization steps can be conducted on available integrated processing platforms.

Abstract: The present invention provides a process sequence and related hardware for filling a hole with copper. The sequence comprises first forming a reliable barrier layer in the hole to prevent diffusion of the copper into the dielectric layer through which the hole is formed. One sequence comprises forming a generally conformal barrier layer over a patterned dielectric, etching the bottom of the hole, depositing a second barrier, and then filling the hole with copper. An alternative sequence comprises depositing a first barrier layer over a blanket dielectric layer, forming a hole through both the barrier layer and the dielectric layer, depositing a generally conformal second barrier layer in the hole, removing the barrier layer from the bottom of the hole, and selectively filling the hole with copper.

Abstract: The present invention provides a process sequence and related hardware for filling a hole with copper. The sequence comprises first forming a reliable barrier layer in the hole to prevent diffusion of the copper into the dielectric layer through which the hole is formed. One sequence comprises forming a generally conformal barrier layer over a patterned dielectric, etching the bottom of the hole, depositing a second barrier, and then filling the hole with copper. An alternative sequence comprises depositing a first barrier layer over a blanket dielectric layer, forming a hole through both the barrier layer and the dielectric layer, depositing a generally conformal second barrier layer in the hole, removing the barrier layer from the bottom of the hole, and selectively filling the hole with copper.

Abstract: A method of forming a titanium silicide nitride (TiSiN) layer is described. A titanium nitride (TiN) layer is deposited on a substrate, the process chamber is purged to remove reaction by-products therefrom and than the titanium nitride (TiN) layer is exposed to a silicon-containing gas to form the titanium suicide nitride (TiSiN) layer. Alternatively, the substrate may be exposed to the silicon-containing gas in a process chamber different from the one used for the titanium nitride (TiN) layer deposition.

Abstract: A method for processing a substrate comprising the formation of a metal nitride/metal stack suitable for use as a barrier/liner for sub-0.18 &mgr;m device fabrication. After a metal nitride layer is deposited upon a metal layer, the metal nitride layer is exposed to a treatment step in a nitrogen-containing environment, e.g., a plasma. The plasma treatment modifies the entire metal nitride layer and a top portion of the underlying metal layer. The plasma adds nitrogen to the top portion of the metal layer, resulting in the formation of a nitrated-metal layer. Aside from reducing the microstructure mismatch across the nitride-metal interface, the plasma treatment also densifies and reduces impurities from the deposited nitride layer. The resulting nitride/metal stack exhibits improved film properties, including enhanced adhesion and barrier characteristics. A composite nitride layer of a desired thickness can also be formed by repeating the deposition and treatment cycles of thinner component nitride layers.

Abstract: The present invention is an apparatus and method for semi-selectively depositing a material on a substrate by chemical vapor deposition to form continuous, void-free contact holes or vias in sub-half micron applications. An insulating layer is preferentially deposited on the field of a substrate to delay or inhibit nucleation of metal on the field. A CVD metal is then deposited onto the substrate and grows selectively in the contact hole or via where a barrier layer serves as a nucleation layer. The process is preferably carried out in a multi-chamber system that includes both PVD and CVD processing chambers so that once the substrate is introduced into a vacuum environment, the filling of contact holes and vias occurs without the formation of an oxide layer on a patterned substrate.

Abstract: The present invention provides a method and apparatus for forming reliable interconnects in which the overlap of the line over the plug or via is minimized or eliminated. In one aspect, a barrier plug comprised of a conductive material, such as tungsten, is deposited over the via to provide an etch stop during line etching and to prevent diffusion of the metal, such as copper, into the surrounding dielectric material if the line is misaligned over the via. Additionally, the barrier plug prevents an overall reduction in resistance of the interconnect and enables reactive ion etching to be employed to form the metal line. In another aspect, reactive ion etching techniques are employed to selectively etch the metal line and the barrier layer to provide a controlled etching process which exhibits selectivity for the metal line, then the barrier and then the via or plug.

Abstract: The present invention provides a method and apparatus for forming reliable interconnects in which the overlap of the line over the plug or via is minimized or eliminated. In one aspect, a barrier plug comprised of a conductive material, such as tungsten, is deposited over the via to provide an etch stop during line etching and to prevent diffusion of the metal, such as copper, into the surrounding dielectric material if the line is misaligned over the via. Additionally, the barrier plug prevents an overall reduction in resistance of the interconnect and enables reactive ion etching to be employed to form the metal line. In another aspect, reactive ion etching techniques are employed to selectively etch the metal line and the barrier layer to provide a controlled etching process which exhibits selectivity for the metal line, then the barrier and then the via or plug.

Abstract: The present invention relates generally to an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD metal layer is substantially void-free.

Abstract: The present invention provides a method and apparatus for filling contacts, vias, trenches, and other patterns, in a substrate surface, particularly patterns having high aspect ratios. Generally, the present invention provides a method for removing oxygen from the surface of an oxidized metal layer prior to deposition of a subsequent metal. The oxidized metal is treated with a plasma consisting of nitrogen, hydrogen, or a mixture thereof. In one aspect of the invention, the metal layer is Ti, TiN, Ta, TaN, Ni, NiV, or V, and a subsequent wetting layer is deposited using either CVD techniques or electroplating, such as CVD aluminum (Al) or electroplating of copper (Cu). The metal layer can be exposed to oxygen or the atmosphere and then treated with a plasma of nitrogen and/or hydrogen in two or more cycles to remove or reduce oxidation of the surface of the metal layer and nucleate the growth of a subsequent metal layer thereon.

Abstract: The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates a barrier layer deposited on all exposed surface of a dielectric layer which contains a dual damascene via and wire definition. A conductive metal is deposited on the barrier layer using two or more deposition methods to fill the via and wire definition prior to planarization. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD Al via plugs, and a reduced number of process steps to achieve such integration.

Abstract: The invention generally provides an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free interconnections in high aspect ratio, sub-half micron applications. The invention provides a multi-step PVD process in which the plasma power is varied for each of the steps to obtain favorable fill characteristics as well as good reflectivity, morphology and throughput. The initial plasma powers are relatively low to ensure good, void-free filling of the aperture and, then, the plasma powers are increased to obtain the desired reflectivity and morphology characteristics. The invention provides an aperture filling process comprising physical vapor depositing a metal over the substrate and varying the plasma power during the physical vapor deposition. Preferably, the plasma power is varied from a first discrete low plasma power to a second discrete high plasma power.

Abstract: The present invention relates generally to an improved process for providing complete via fill on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer, such as CVD Al or CVD Cu, is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD Cu. Next, a PVD Cu is deposited onto the previously formed CVD Cu layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD Cu layer is substantially void-free.