Abstract: The present invention provides a method and apparatus for forming an interconnect with application in small feature sizes (such as quarter micron widths) having high aspect ratios. Generally, the present invention provides a method and apparatus for depositing a wetting layer for subsequent physical vapor deposition to fill the interconnect. In one aspect of the invention, the wetting layer is a metal layer deposited using either CVD techniques or electroplating, such as CVD aluminum (Al). The wetting layer is nucleated using an ultra-thin layer, denoted as .di-elect cons. layer, as a nucleation layer. The .di-elect cons. layer is preferably comprised of a material such as Ti, TiN, Al, Ti/TiN, Ta, TaN, Cu, a flush of TDMAT or the like. The .di-elect cons. layer may be deposited using PVD or CVD techniques, preferably PVD techniques to improve film quality and orientation within the feature. Contrary to conventional wisdom, the .di-elect cons.

Abstract: The present invention generally provides a precleaning process prior to metallization for submicron features on substrates. The method includes cleaning the submicron features with radicals from a plasma of a reactive gas such as oxygen, a mixture of CF.sub.4 /O.sub.2, or a mixture of He/NF.sub.3, wherein the plasma is preferably generated by a remote plasma source and the radicals are delivered to a chamber in which the substrate is disposed. Native oxides remaining in the submicron features are preferably reduced in a second step by treatment with radicals from a plasma containing hydrogen. Following the first or both precleaning steps, the features can be filled with metal by available metallization techniques which typically include depositing a barrier/liner layer on exposed dielectric surfaces prior to deposition of aluminum, copper, or tungsten. The precleaning and metallization steps can be conducted on available integrated processing platforms.

Abstract: The present invention generally provides a method for processing a substrate having exposed surfaces of titanium and/or silicon prior to deposition of aluminum. The substrate is positioned adjacent a process zone which provides a nitrogen plasma so that exposed areas of titanium and silicon on the substrate are stuffed with nitrogen to form titanium nitride (TiN) and various compounds of silicon and nitrogen (Si.sub.x N.sub.y), respectively. The nitrogen treated surfaces, i.e, TiN and silicon/nitrogen compounds, are resistant to interaction with aluminum. In this manner, the formation of electrically insulating TiAl.sub.3 and/or the spiking of silicon is reduced or eliminated.

Abstract: The present invention is to a chemical vapor deposition process for depositing a substantially planar, highly reflective layer on a substrate, and is particularly useful for filling high aspect ratio holes in the substrate with metal-containing material. The substrate is placed in a process zone, and successive seeding and oriented crystal growth stages are performed on the substrate. In the seeding stage, the substrate is heated to temperatures T.sub.s, within a first lower range of temperatures .DELTA. T.sub.s, and a seeding gas is introduced into the process zone. The seeding gas deposits a substantially continuous, non-granular, and planar seeding layer on the substrate. Thereafter, in an oriented crystal growth stage, the substrate is maintained at deposition temperatures T.sub.d, within a second higher range of temperatures .DELTA. T.sub.D, and deposition gas is introduced into the process zone.

Abstract: The present invention is a method for semi-selectively depositing a material on a substrate by chemical vapor deposition to form continuous, void-free contact holes or vias in sub-half micron applications. An insulating layer is preferentially deposited on the field of a substrate to delay or inhibit nucleation of metal on the field. A CVD metal is then deposited onto the substrate and grows selectively in the contact hole or via where a barrier layer serves as a nucleation layer. The process is preferably carried out in a multi-chamber system that includes both PVD and CVD processing chambers so that once the substrate is introduced into a vacuum environment, the filling of contact holes and vias occurs without the formation of an oxide layer on a patterned substrate.

Abstract: The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates a barrier layer deposited on all exposed surface of a dielectric layer which contains a dual damascene via and wire definition. A conductive metal is deposited on the barrier layer using two or more deposition methods to fill the via and wire definition prior to planarization. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD Al via plugs, and a reduced number of process steps to achieve such integration.

Abstract: The present invention relates generally to an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD metal layer is substantially void-free.

Abstract: A collimator having a particle getter function, and a thin-film forming apparatus equipped with the collimator disposed between a target and a wafer. The collimator is fabricated by assembling particle getter sheets into a lattice, honeycomb, or other structure having a number of rows of openings and fixing the assembly into a frame. The particle getter sheets refers collectively to sheets and plates to be assembled integrally to provide a surface having excellent particle capturing and holding actions. Typically, the collimator is a lattice assembly of embossed, slitted particle getter sheets. The film deposited on the collimator is kept from peeling off, without deteriorating the collimator performance.