Patents by Inventor Roel Gronheid

Roel Gronheid has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190157086
    Abstract: A method for forming a film with an annealing step and a deposition step is disclosed. The method comprises an annealing step for inducing self-assembly or alignment within a polymer. The method also comprises a selective deposition step in order to enable selective deposition on a polymer.
    Type: Application
    Filed: January 23, 2019
    Publication date: May 23, 2019
    Inventors: Jan Willem MAES, Werner KNAEPEN, Roel GRONHEID, Arjun SINGH
  • Publication number: 20190155159
    Abstract: A method of forming a directed self-assembled (DSA) layer on a substrate by: providing a substrate; applying a layer comprising a self-assembly material on the substrate; and annealing of the self-assembly material of the layer to form a directed self-assembled layer by providing a controlled temperature and gas environment around the substrate. The controlled gas environment comprises molecules comprising an oxygen element with a partial pressure between 10-2000 Pa.
    Type: Application
    Filed: April 7, 2017
    Publication date: May 23, 2019
    Inventors: Werner Knaepen, Jan Willem Maes, Maarten Stokhof, Roel Gronheid, Hari Pathangi Sriraman
  • Publication number: 20190074186
    Abstract: A mask structure and a method for manufacturing a mask structure for a lithography process is provided. The method includes providing a substrate covered with an absorber layer on a side thereof; providing a patterned layer over the absorber layer, the patterned layer comprising at least one opening; and forming at least one assist mask feature in the at least one opening, wherein the at least one assist mask feature is formed by performing a directed self-assembly (DSA) patterning process comprising providing a BCP material in the at least one opening and inducing phase separation of a BCP material into a first component and a second component, the first component being the at least one assist mask feature and being periodically distributed with respect to the second component.
    Type: Application
    Filed: August 30, 2018
    Publication date: March 7, 2019
    Applicants: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&D
    Inventors: Emily Gallagher, Roel Gronheid, Jan Doise, Iacopo Mochi
  • Publication number: 20190049858
    Abstract: Methods are provided for designing metrology targets and estimating the uncertainty error of metrology metric values with respect to stochastic noise such as line properties (e.g., line edge roughness, LER). Minimal required dimensions of target elements may be derived from analysis of the line properties and uncertainty error of metrology measurements, by either CDSEM (critical dimension scanning electron microscopy) or optical systems, with corresponding targets. The importance of this analysis is emphasized in view of the finding that stochastic noise may have increased importance with when using more localized models such as CPE (correctables per exposure). The uncertainty error estimation may be used for target design, enhancement of overlay estimation and evaluation of measurement reliability in multiple contexts.
    Type: Application
    Filed: February 27, 2018
    Publication date: February 14, 2019
    Inventors: Evgeni GUREVICH, Michael E. ADEL, Roel GRONHEID, Yoel FELER, Vladimir LEVINSKI, Dana KLEIN, Sharon AHARON
  • Patent number: 10204782
    Abstract: A method for forming a film with an annealing step and a deposition step is disclosed. The method comprises an annealing step for inducing self-assembly or alignment within a polymer. The method also comprises a selective deposition step in order to enable selective deposition on a polymer.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: February 12, 2019
    Assignees: IMEC vzw, ASM IP HOLDING B.V.
    Inventors: Jan Willem Maes, Werner Knaepen, Roel Gronheid, Arjun Singh
  • Patent number: 10192956
    Abstract: A method for producing fin structures, using Directed Self Assembly (DSA) lithographic patterning, in an area of a semiconductor substrate includes providing a semiconductor substrate covered with a shallow trench isolation (STI) layer stack on a side thereof; defining a fin area on that side of the substrate by performing a lithographic patterning step other than DSA, wherein the fin structures will be produced in the fin area; and producing the fin structures in the semiconductor substrate within the fin area according to a predetermined fin pattern using DSA lithographic patterning. The disclosure also relates to associated semiconductor structures.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: January 29, 2019
    Assignee: IMEC VZW
    Inventors: Boon Teik Chan, Safak Sayan, Min-Soo Kim, Doni Parnell, Roel Gronheid
  • Patent number: 10186459
    Abstract: The present disclosure relates to methods and structures that involve the use of directed self-assembly to selectively remove at least one fin or fin section from a pattern of parallel fins in a semiconductor structure.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: January 22, 2019
    Assignee: IMEC VZW
    Inventors: Roel Gronheid, Vladimir Machkaoutsan
  • Patent number: 10048212
    Abstract: A method for evaluating the quality of a directed self-assembling method used for generating directed self-assembling patterns. The method for evaluating comprises obtaining at least one set of parameter values for a parameterized set of processing steps and material properties characterizing the directed self-assembling method, thus characterizing a specific directed self-assembling method used for generating a directed self-assembled pattern. The method furthermore comprises obtaining a scattered radiation pattern on the directed self-assembled pattern obtained using the directed self-assembling method characterized by the set of parameter values, thus obtaining scattered radiation pattern results for the directed self-assembled pattern. The method furthermore comprises determining based on the scattered radiation pattern results a qualification score and correlating the qualification score with the set of parameter values.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: August 14, 2018
    Assignee: IMEC VZW
    Inventors: Roel Gronheid, Lieve Van Look, Paulina Alejandra Rincon Delgadillo
  • Publication number: 20180173109
    Abstract: An example embodiment relates to a method for making a mask layer. The method may include providing a patterned layer on a substrate, the patterned layer including at least a first set of lines of an organic material of a first nature, the lines having a line height, a first line width roughness, and being separated either by voids or by a material of a second nature. The method may further include infiltrating at least a top portion of the first set of lines with a metal or ceramic material. The method may further include removing the organic material by oxidative plasma etching, thereby forming a second set of lines of metal or ceramic material on the substrate, the second set of lines having a second line width roughness, smaller than the first line width roughness.
    Type: Application
    Filed: November 15, 2017
    Publication date: June 21, 2018
    Applicants: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&D
    Inventors: Roel Gronheid, Arjun Singh, Werner Knaepen
  • Publication number: 20180076092
    Abstract: The present disclosure relates to methods and structures that involve the use of directed self-assembly to selectively remove at least one fin or fin section from a pattern of parallel fins in a semiconductor structure.
    Type: Application
    Filed: September 14, 2017
    Publication date: March 15, 2018
    Applicant: IMEC VZW
    Inventors: Roel Gronheid, Vladimir Machkaoutsan
  • Publication number: 20170330760
    Abstract: The present disclosure relates to a method for manufacturing pillar or hole structures in a layer of semiconductor device, and associated semiconductor structure. At least one embodiment relates to a method for manufacturing pillar structures in a layer of a semiconductor device. The pillar structures are arranged at positions forming a hexagonal matrix configuration. The method includes embedding alignment pillar structures in a backfill brush polymer layer. The method also includes providing a BCP layer on a substantially planar surface defined by an upper surface of the alignment pillar structures and the backfill brush polymer layer. Further, the method includes inducing polymer microphase separation of the BCP polymer layer into pillar structures of a first component of the BCP polymer layer embedded in a second component of the BCP polymer layer.
    Type: Application
    Filed: October 28, 2015
    Publication date: November 16, 2017
    Applicants: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&D
    Inventors: Arjun SINGH, Roel GRONHEID
  • Publication number: 20170301542
    Abstract: A method for forming a film with an annealing step and a deposition step is disclosed. The method comprises an annealing step for inducing self-assembly or alignment within a polymer. The method also comprises a selective deposition step in order to enable selective deposition on a polymer.
    Type: Application
    Filed: April 18, 2016
    Publication date: October 19, 2017
    Inventors: Jan Willem MAES, Werner KNAEPEN, Roel GRONHEID, Arjun Singh
  • Publication number: 20160322461
    Abstract: A method for producing fin structures, using Directed Self Assembly (DSA) lithographic patterning, in an area of a semiconductor substrate includes providing a semiconductor substrate covered with a shallow trench isolation (STI) layer stack on a side thereof; defining a fin area on that side of the substrate by performing a lithographic patterning step other than DSA, wherein the fin structures will be produced in the fin area; and producing the fin structures in the semiconductor substrate within the fin area according to a predetermined fin pattern using DSA lithographic patterning. The disclosure also relates to associated semiconductor structures.
    Type: Application
    Filed: July 7, 2016
    Publication date: November 3, 2016
    Applicant: IMEC VZW
    Inventors: Boon Teik Chan, Safak Sayan, Min-Soo Kim, Doni Parnell, Roel Gronheid
  • Patent number: 9391141
    Abstract: A method for producing fin structures, using Directed Self Assembly (DSA) lithographic patterning, in an area of a semiconductor substrate includes providing a semiconductor substrate covered with a shallow trench isolation (STI) layer stack on a side thereof; defining a fin area on that side of the substrate by performing a lithographic patterning step other than DSA, wherein the fin structures will be produced in the fin area; and producing the fin structures in the semiconductor substrate within the fin area according to a predetermined fin pattern using DSA lithographic patterning. The disclosure also relates to associated semiconductor structures.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: July 12, 2016
    Assignee: IMEC VZW
    Inventors: Boon Teik Chan, Safak Sayan, Min-Soo Kim, Doni Parnell, Roel Gronheid
  • Publication number: 20150276624
    Abstract: A method for evaluating the quality of a directed self-assembling method used for generating directed self-assembling patterns. The method for evaluating comprises obtaining at least one set of parameter values for a parameterized set of processing steps and material properties characterizing the directed self-assembling method, thus characterizing a specific directed self-assembling method used for generating a directed self-assembled pattern. The method furthermore comprises obtaining a scattered radiation pattern on the directed self-assembled pattern obtained using the directed self-assembling method characterized by the set of parameter values, thus obtaining scattered radiation pattern results for the directed self-assembled pattern. The method furthermore comprises determining based on the scattered radiation pattern results a qualification score and correlating the qualification score with the set of parameter values.
    Type: Application
    Filed: March 31, 2015
    Publication date: October 1, 2015
    Applicants: Katholieke Universiteit Leuven, KU LEUVEN R&D, IMEC VZW
    Inventors: Roel Gronheid, Lieve Van Look, Paulina Alejandra Rincon Delgadillo
  • Publication number: 20150243509
    Abstract: A method for producing fin structures, using Directed Self Assembly (DSA) lithographic patterning, in an area of a semiconductor substrate includes providing a semiconductor substrate covered with a shallow trench isolation (STI) layer stack on a side thereof; defining a fin area on that side of the substrate by performing a lithographic patterning step other than DSA, wherein the fin structures will be produced in the fin area; and producing the fin structures in the semiconductor substrate within the fin area according to a predetermined fin pattern using DSA lithographic patterning. The disclosure also relates to associated semiconductor structures.
    Type: Application
    Filed: February 23, 2015
    Publication date: August 27, 2015
    Applicant: IMEC VZW
    Inventors: Boon Teik Chan, Safak Sayan, Min-Soo Kim, Doni Parnell, Roel Gronheid
  • Patent number: 9041164
    Abstract: In one aspect, a method is disclosed that includes providing a substrate having a topography that comprises a relief and providing an anti-reflective film conformally over the substrate using a molecular layer deposition step. The anti-reflective film may be formed of a compound selected from the group consisting of: (i) an organic compound chemically bound to an inorganic compound, where one of the organic compound and the inorganic compound is bound to the substrate and where the organic compound absorbs light at at least one wavelength selected in the range 150-500 nm, or (ii) a monodisperse organic compound absorbing light at at least one wavelength selected in the range 150-500 nm. The method further includes providing a photoresist layer on the anti-reflective film.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: May 26, 2015
    Assignee: IMEC
    Inventors: Roel Gronheid, Christoph Adelmann, Annelies Delabie, Gustaf Winroth
  • Publication number: 20140231968
    Abstract: In one aspect, a method is disclosed that includes providing a substrate having a topography that comprises a relief and providing an anti-reflective film conformally over the substrate using a molecular layer deposition step. The anti-reflective film may be formed of a compound selected from the group consisting of: (i) an organic compound chemically bound to an inorganic compound, where one of the organic compound and the inorganic compound is bound to the substrate and where the organic compound absorbs light at at least one wavelength selected in the range 150-500 nm, or (ii) a monodisperse organic compound absorbing light at at least one wavelength selected in the range 150-500 nm. The method further includes providing a photoresist layer on the anti-reflective film.
    Type: Application
    Filed: February 19, 2014
    Publication date: August 21, 2014
    Applicant: IMEC
    Inventors: Roel Gronheid, Christoph Adelmann, Annelies Delabie, Gustaf Winroth
  • Patent number: 8257911
    Abstract: A method for patterning a substrate is described. In particular, the invention relates to a method for double patterning a substrate using dual tone development. Further, the invention relates to optimizing a dual tone development process.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: September 4, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Roel Gronheid, Sophie Bernard, Carlos A. Fonseca, Mark Somervell, Steven Scheer
  • Patent number: 7695877
    Abstract: One inventive aspect relates to a method of lithographic processing of a device). The method may be performed using a lithographic processing system and applying a reticle). Lithographic processing of a device typically is characterized by focus conditions, a set of selectable lithographic processing system parameter values and selectable reticle parameter values. The method of configuring the lithographic processing comprises receiving values for the lithographic processing system parameters and for the reticle parameters. The method further comprises receiving focus conditions for the lithographic processing, the focus conditions allowing separation of image performance effects due to lithographic processing system aberrations and image performance effects due to reticle shadowing effects. The method further comprises determining image performance effects due to lithographic processing system aberrations and the image performance due to reticle shadowing effects.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: April 13, 2010
    Assignee: IMEC
    Inventors: Leonardus Leunissen, Roel Gronheid