Patents by Inventor Roelf Anco Jacob Groenhuis
Roelf Anco Jacob Groenhuis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10315821Abstract: One example discloses a component carrier, including: a cavity; wherein the cavity includes a set of cavity registration features configured to engage with a set of component registration features on a component; and wherein the cavity registration features are within the cavity.Type: GrantFiled: November 15, 2016Date of Patent: June 11, 2019Assignee: NXP B.V.Inventors: Jeroen Johannes Maria Zaal, Roelf Anco Jacob Groenhuis, Leo van Gemert, Caroline Catharina Maria Beelen-Hendrikx
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Patent number: 10177111Abstract: Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces of the wafer substrate. By defining trenches in saw lanes between active device die, additional resilient material may be placed therein. In an example embodiment, after the active device die are separated into individual product devices, the resulting product device has coverage on the front-side surface, back-side surface, and the four vertical faces of the encapsulated active device die. The front-side surface has exposed contact areas so that the product device may be attached to an end user's system circuit board. Further, the resilient coating protects the encapsulated active device die from damage during assembly.Type: GrantFiled: March 6, 2017Date of Patent: January 8, 2019Assignee: NXP B.V.Inventors: Tonny Kamphuis, Leonardus Antonius Elisabeth van Gemert, Roelf Anco Jacob Groenhuis, Caroline Catharina Maria Beelen-Hendrikx, Jetse de Witte, Franciscus Henrikus Martinus Swartjes
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Publication number: 20180134473Abstract: One example discloses a component carrier, including: a cavity; wherein the cavity includes a set of cavity registration features configured to engage with a set of component registration features on a component; and wherein the cavity registration features are within the cavity.Type: ApplicationFiled: November 15, 2016Publication date: May 17, 2018Inventors: Jeroen Johannes Maria Zaal, Roelf Anco Jacob Groenhuis, Leo van Gemert, Caroline Catharina Maria Beelen-Hendrikx
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Patent number: 9842776Abstract: Integrated circuit dies within a semiconductor wafer are separated using an approach that may facilitate mitigation of warpage, cracking and other undesirable aspects. As may be implemented in accordance with one or more embodiments, a semiconductor wafer is provided with a plurality of integrated circuit dies and first and second opposing surfaces, and with the second surface of the wafer being ground. A first mold compound is applied to the ground second surface, and the integrated circuit dies are separated along saw lanes while using the first mold compound to hold the dies in place. The integrated circuit dies are encapsulated with the mold compounds, by applying the second mold compound to the first surface and along sidewalls of the integrated circuit dies.Type: GrantFiled: January 13, 2016Date of Patent: December 12, 2017Assignee: NXP B.V.Inventors: John Suman Nakka, Tonny Kamphuis, Roelf Anco Jacob Groenhuis
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Publication number: 20170200646Abstract: Integrated circuit dies within a semiconductor wafer are separated using an approach that may facilitate mitigation of warpage, cracking and other undesirable aspects. As may be implemented in accordance with one or more embodiments, a semiconductor wafer is provided with a plurality of integrated circuit dies and first and second opposing surfaces, and with the second surface of the wafer being ground. A first mold compound is applied to the ground second surface, and the integrated circuit dies are separated along saw lanes while using the first mold compound to hold the dies in place. The integrated circuit dies are encapsulated with the mold compounds, by applying the second mold compound to the first surface and along sidewalls of the integrated circuit dies.Type: ApplicationFiled: January 13, 2016Publication date: July 13, 2017Inventors: John Suman Nakka, Tonny Kamphuis, Roelf Anco Jacob Groenhuis
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Patent number: 9704823Abstract: Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces of the wafer substrate. By defining trenches in saw lanes between active device die, additional resilient material may be placed therein. In an example embodiment, after the active device die are separated into individual product devices, the resulting product device has coverage on the front-side surface, back-side surface, and the four vertical faces of the encapsulated active device die. The front-side surface has exposed contact areas so that the product device may be attached to an end user's system circuit board. Further, the resilient coating protects the encapsulated active device die from damage during assembly.Type: GrantFiled: October 29, 2015Date of Patent: July 11, 2017Assignee: NXP B.V.Inventors: Tonny Kamphuis, Roelf Anco Jacob Groenhuis, Leonardus Antonius Elisabeth van Gemert, Caroline Catharina Maria Beelen-Hendrikx, Jetse de Witte, Franciscus Henrikus Martinus Swartjes
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Publication number: 20170179076Abstract: Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces of the wafer substrate. By defining trenches in saw lanes between active device die, additional resilient material may be placed therein. In an example embodiment, after the active device die are separated into individual product devices, the resulting product device has coverage on the front-side surface, back-side surface, and the four vertical faces of the encapsulated active device die. The front-side surface has exposed contact areas so that the product device may be attached to an end user's system circuit board. Further, the resilient coating protects the encapsulated active device die from damage during assembly.Type: ApplicationFiled: March 6, 2017Publication date: June 22, 2017Inventors: Tonny Kamphuis, Leonardus Antonius Elisabeth van Gemert, Roelf Anco Jacob Groenhuis, Caroline Catharina Maria Beelen-Hendrikx, Jetse de Witte, Franciscus Henrikus Martinus Swartjes
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Patent number: 9466585Abstract: Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces of the wafer substrate. By defining trenches in saw lanes between active device die, additional resilient material may be placed therein. In an example embodiment, after the active device die are separated into individual product devices, the resulting product device has coverage on the front-side surface, back-side surface, and the four vertical faces of the encapsulated active device die. The front-side surface has exposed contact areas so that the product device may be attached to an end user's system circuit board. Further, the resilient coating protects the encapsulated active device die from damage during assembly.Type: GrantFiled: October 29, 2015Date of Patent: October 11, 2016Assignee: NXP B.V.Inventors: Tonny Kamphuis, Leonardus Antonius Elisabeth van Gemert, Roelf Anco Jacob Groenhuis, Caroline Catharina Maria Beelen-Hendrikx, Franciscus Henrikus Martinus Swartjes, Jetse de Witte
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Publication number: 20160276176Abstract: Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces of the wafer substrate. By defining trenches in saw lanes between active device die, additional resilient material may be placed therein. In an example embodiment, after the active device die are separated into individual product devices, the resulting product device has coverage on the front-side surface, back-side surface, and the four vertical faces of the encapsulated active device die. The front-side surface has exposed contact areas so that the product device may be attached to an end user's system circuit board. Further, the resilient coating protects the encapsulated active device die from damage during assembly.Type: ApplicationFiled: October 29, 2015Publication date: September 22, 2016Inventors: Tonny Kamphuis, Roelf Anco Jacob Groenhuis, Leonardus Antonius Elisabeth van Gemert, Caroline Catharina Maria Beelen-Hendrikx, Jetse de Witte, Franciscus Henrikus Martinus Swartjes
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Publication number: 20160276306Abstract: Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces of the wafer substrate. By defining trenches in saw lanes between active device die, additional resilient material may be placed therein. In an example embodiment, after the active device die are separated into individual product devices, the resulting product device has coverage on the front-side surface, back-side surface, and the four vertical faces of the encapsulated active device die. The front-side surface has exposed contact areas so that the product device may be attached to an end user's system circuit board. Further, the resilient coating protects the encapsulated active device die from damage during assembly.Type: ApplicationFiled: October 29, 2015Publication date: September 22, 2016Inventors: Tonny Kamphuis, Leonardus Antonius Elisabeth van Gemert, Roelf Anco Jacob Groenhuis, Caroline Catharina Maria Beelen-Hendrikx, Franciscus Henrikus Martinus Swartjes, Jetse de Witte
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Patent number: 9418918Abstract: There is disclosed a lead for connection to a semiconductor device die, the lead comprising a clip portion. The clip portion comprises a major surface having two or more protrusions extending therefrom for connection to a bond pad of the semiconductor device die.Type: GrantFiled: March 25, 2015Date of Patent: August 16, 2016Assignee: NXP B.V.Inventors: Roelf Anco Jacob Groenhuis, Tim Boettcher
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Patent number: 9418919Abstract: Consistent with an example embodiment, there is surface-mountable non-leaded chip carrier for a semiconductor device. The device comprises a first contact. A second contact is relative to the first contact; the second contact has a split therein to provide first and second portions of the second contact arranged relative to one another to lessen tilting of a soldering condition involving attachment of the chip carrier to a printed circuit board.Type: GrantFiled: January 14, 2011Date of Patent: August 16, 2016Assignee: NXP B.V.Inventors: Roelf Anco Jacob Groenhuis, Markus Björn Erik Noren, Fei-ying Wong, Hei-ming Shiu
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Publication number: 20160211197Abstract: Consistent with an example embodiment, there is surface-mountable non-leaded chip carrier for a semiconductor device. The device comprises a first contact. A second contact is relative to the first contact; the second contact has a split therein to provide first and second portions of the second contact arranged relative to one another to lessen tilting of a soldering condition involving attachment of the chip carrier to a printed circuit board.Type: ApplicationFiled: January 14, 2011Publication date: July 21, 2016Applicant: NXP B.V.Inventors: Roelf Anco Jacob GROENHUIS, Markus Björn Erik NOREN, Fei-ying WONG, Hei-ming SHIU
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Patent number: 9263335Abstract: Disclosed is a discrete semiconductor device package (100) comprising a semiconductor die (110) having a first surface and a second surface opposite said first surface carrying a contact (112); a conductive body (120) on said contact; an encapsulation material (130) laterally encapsulating said conductive body; and a capping member (140, 610) such as a solder cap, a further semiconductor die or a combination thereof in conductive contact with the solder portion, said solder cap extending over the encapsulation material. A further solder cap (150) may be provided over the first surface. A method of manufacturing such a discrete semiconductor device package is also disclosed.Type: GrantFiled: January 28, 2015Date of Patent: February 16, 2016Assignee: NXP B.V.Inventors: Tim Boettcher, Sven Walczyk, Roelf Anco Jacob Groenhuis, Rolf Brenner, Emiel De Bruin
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Publication number: 20160005679Abstract: Consistent with an example embodiment, there is a method for packaging an integrated circuit (IC) device. The method comprises attaching a lead frame to the carrier tape; the lead frame has an array of device positions on the carrier tape and pad landings surround the device positions for making electrical connections to the plurality of active device die. A plurality of active device die are mounted on the carrier tape within the array of device positions; each said active device die has bond pads, each of said active device die has been subjected to back-grinding to a prescribed thickness and has a solderable conductive surface on its underside. On the bond pads, the plurality of active devices are wire bonded to the pad landings on the lead frame. The lead frame and wire bonded active devices are encapsulated, leaving the solderable die backside and lead frame backside exposed.Type: ApplicationFiled: July 2, 2014Publication date: January 7, 2016Inventors: Emil Casey Israel, Leonardus Antonius Elisabeth van Gemert, Roelf Anco Jacob Groenhuis
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Patent number: 9222989Abstract: A sensor package includes a lead frame with a first portion extending and a second portion extending in a direction inclined with respect to the first potion. The sensor package also includes an application specific integrated circuit and a magneto resistive sensor and a ferrite provided with a molding body.Type: GrantFiled: January 15, 2014Date of Patent: December 29, 2015Assignee: NXP B.V.Inventors: Paulus Martinus Catharina Hesen, Roelf Anco Jacob Groenhuis, Johannes Wilhelmus Dorotheus Bosch
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Publication number: 20150287666Abstract: There is disclosed a lead for connection to a semiconductor device die, the lead comprising a clip portion. The clip portion comprises a major surface having two or more protrusions extending therefrom for connection to a bond pad of the semiconductor device die.Type: ApplicationFiled: March 25, 2015Publication date: October 8, 2015Inventors: Roelf Anco Jacob Groenhuis, Tim Boettcher
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Publication number: 20150140739Abstract: Disclosed is a discrete semiconductor device package (100) comprising a semiconductor die (110) having a first surface and a second surface opposite said first surface carrying a contact (112); a conductive body (120) on said contact; an encapsulation material (130) laterally encapsulating said conductive body; and a capping member (140, 610) such as a solder cap, a further semiconductor die or a combination thereof in conductive contact with the solder portion, said solder cap extending over the encapsulation material. A further solder cap (150) may be provided over the first surface. A method of manufacturing such a discrete semiconductor device package is also disclosed.Type: ApplicationFiled: January 28, 2015Publication date: May 21, 2015Inventors: Tim BOETTCHER, Sven WALCZYK, Roelf Anco Jacob GROENHUIS, Rolf BRENNER, Emiel DE BRUIN
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Patent number: 8981566Abstract: Disclosed is a discrete semiconductor device package (100) comprising a semiconductor die (110) having a first surface and a second surface opposite said first surface carrying a contact (112); a conductive body (120) on said contact; an encapsulation material (130) laterally encapsulating said conductive body; and a capping member (140, 610) such as a solder cap, a further semiconductor die or a combination thereof in conductive contact with the solder portion, said solder cap extending over the encapsulation material. A further solder cap (150) may be provided over the first surface. A method of manufacturing such a discrete semiconductor device package is also disclosed.Type: GrantFiled: May 8, 2013Date of Patent: March 17, 2015Assignee: NXP B.V.Inventors: Tim Boettcher, Sven Walczyk, Roelf Anco Jacob Groenhuis, Rolf Brenner, Emiel De Bruin
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Patent number: 8884410Abstract: A method for manufacturing a microelectronic package (1) comprises the steps of providing at least two members (10, 11, 16) comprising electrically conductive material; providing a microelectronic device (15); placing the electrically conductive members (10, 11, 16) and the microelectronic device (15) in predetermined positions with respect to each other, and establishing electrical connections between each of the electrically conductive members (10, 11, 16) and the microelectronic device (15); and providing a non-conductive material for encapsulating the microelectronic device (15) and a portion of the electrically conductive members (10, 11, 16) connected thereto. The electrically conductive members (10, 11, 16) are intended to be used for realizing contact of the microelectronic device (15) arranged inside the package (1) to the external world.Type: GrantFiled: October 16, 2009Date of Patent: November 11, 2014Assignee: NXP B.V.Inventors: Peter Wilhelmus Maria Van De Water, Paulus Martinus Catharina Hesen, Roelf Anco Jacob Groenhuis