Patents by Inventor Roger A. Chang

Roger A. Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10676671
    Abstract: The present invention relates to a method of reducing ODF mura in liquid crystal (LC) displays of the polymer sustained alignment (PSA) type and to PSA LC displays made by this method.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: June 9, 2020
    Assignee: Merck Patent GmbH
    Inventors: Leo Weegels, Roger Chang, Ky Lin
  • Patent number: 10571463
    Abstract: Materials, systems and methods are provided for qualitative assessment of exposure of a person to ionizing radiation by measuring amounts of the biomarkers, wherein a change compared with corresponding un-irradiated control reference ranges of the biomarkers, provides the assessment, wherein the biomarkers include (i) alpha-1-Antichymotrypsin (ACT), (ii) Fms-related tyrosine kinase 3 ligand (Flt3L), and (iii) one or more additional proteins.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: February 25, 2020
    Assignee: SRI INTERNATIONAL
    Inventors: David E. Cooper, Robert Balog, Polly Chang, Thomas A. Shaler, Hua Lin, Annalisa D'Andrea, Travis Harrison, Roger H. Schmidt, Christina Swanson, Estevan Mendoza, Mark Steele, Pablo E. Garcia
  • Publication number: 20200006548
    Abstract: An embodiment is a semiconductor structure. The semiconductor structure includes a substrate. A fin is on the substrate. The fin includes silicon germanium. An interfacial layer is over the fin. The interfacial layer has a thickness in a range from greater than 0 nm to about 4 nm. A source/drain region is over the interfacial layer. The source/drain region includes silicon germanium.
    Type: Application
    Filed: September 13, 2019
    Publication date: January 2, 2020
    Inventors: Chih-Yun Chin, Chii-Horng Li, Chien-Wei Lee, Hsueh-Chang Sung, Heng-Wen Ting, Roger Tai, Pei-Ren Jeng, Tzu-Hsiang Hsu, Yen-Ru Lee, Yan-Ting Lin, Davie Liu
  • Publication number: 20190378920
    Abstract: An embodiment is a semiconductor structure. The semiconductor structure includes a substrate. A fin is on the substrate. The fin includes silicon germanium. An interfacial layer is over the fin. The interfacial layer has a thickness in a range from greater than 0 nm to about 4 nm. A source/drain region is over the interfacial layer. The source/drain region includes silicon germanium.
    Type: Application
    Filed: June 11, 2018
    Publication date: December 12, 2019
    Inventors: Chih-Yun Chin, Chii-Horng Li, Chien-Wei Lee, Hsueh-Chang Sung, Heng-Wen Ting, Roger Tai, Pei-Ren Jeng, Tzu-Hsiang Hsu, Yen-Ru Lee, Yan-Ting Lin, Davie Liu
  • Patent number: 10483396
    Abstract: An embodiment is a semiconductor structure. The semiconductor structure includes a substrate. A fin is on the substrate. The fin includes silicon germanium. An interfacial layer is over the fin. The interfacial layer has a thickness in a range from greater than 0 nm to about 4 nm. A source/drain region is over the interfacial layer. The source/drain region includes silicon germanium.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: November 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yun Chin, Chii-Horng Li, Chien-Wei Lee, Hsueh-Chang Sung, Heng-Wen Ting, Roger Tai, Pei-Ren Jeng, Tzu-Hsiang Hsu, Yen-Ru Lee, Yan-Ting Lin, Davie Liu
  • Patent number: 10468331
    Abstract: A heat management system may include a die package. The die package may include a housing. The housing may include a housing surface. The housing may include a housing inlet port. The housing inlet port may be in communication with the housing surface. The housing may include a housing outlet port. The housing outlet port may be in communication with the housing surface. The heat management system may include a manifold. The manifold may be configured to couple with the housing. The manifold may include a manifold surface. The manifold surface may be configured to mate with the housing surface. The manifold may include a manifold inlet port. The manifold inlet port may be in communication with the manifold surface. The manifold may include a manifold outlet port. The manifold outlet port may be in communication with the manifold surface.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 5, 2019
    Assignee: Intel Corporation
    Inventors: Je-young Chang, Jae W. Kim, Ravindranath V. Mahajan, Blake Rogers, Devdatta Kulkarni
  • Publication number: 20190221499
    Abstract: A heat management system may include a die package. The die package may include a housing. The housing may include a housing surface. The housing may include a housing inlet port. The housing inlet port may be in communication with the housing surface. The housing may include a housing outlet port. The housing outlet port may be in communication with the housing surface. The heat management system may include a manifold. The manifold may be configured to couple with the housing. The manifold may include a manifold surface. The manifold surface may be configured to mate with the housing surface. The manifold may include a manifold inlet port. The manifold inlet port may be in communication with the manifold surface. The manifold may include a manifold outlet port. The manifold outlet port may be in communication with the manifold surface.
    Type: Application
    Filed: January 12, 2018
    Publication date: July 18, 2019
    Inventors: Je-young Chang, Jae W. Kim, Ravindranath V. Mahajan, Blake Rogers, Devdatta Kulkarni
  • Publication number: 20190175343
    Abstract: Implants or systems of implants and methods apply a selected force vector or a selected combination of force vectors within or across the right atrium, which allow tricuspid valve leaflets to better coapt. The implants or systems of implants and methods make possible rapid deployment, facile endovascular delivery, and full intra-atrial retrievability. The implants or systems of implants and methods also make use of strong fluoroscopic landmarks. The implants or systems of implants and methods make use of an adjustable implant. The implants or systems of implants and methods may utilize a bridge stop to secure the implant.
    Type: Application
    Filed: December 5, 2018
    Publication date: June 13, 2019
    Inventors: Robert T. Chang, Timothy R. Machold, David A. Rahdert, Jason Rogers
  • Publication number: 20180201837
    Abstract: The present invention relates to a method of reducing ODF mura in liquid crystal (LC) displays of the polymer sustained alignment (PSA) type and to PSA LC displays made by this method.
    Type: Application
    Filed: June 23, 2016
    Publication date: July 19, 2018
    Applicant: Merck Patent GmbH
    Inventors: Leo WEEGELS, Roger CHANG, Ky LIN
  • Publication number: 20160230475
    Abstract: A drilling riser buoyancy module comprises two opposite complementary halves each having complementary co-axially extending central opening for a flow line and at least five complementary axially extending secondary openings for receiving auxiliary lines. Each complementary half comprising foam bounded by an interior surface and an exterior surface. A portion of the interior surfaces of complementary halves contact each another.
    Type: Application
    Filed: February 8, 2016
    Publication date: August 11, 2016
    Inventors: Majdi Haddad, Roger Chang, Mark Schlegel, Louis Kabelka
  • Publication number: 20130037745
    Abstract: The present invention relates to a liquid-crystalline medium, characterised in that it contains a polymerisable component (A) containing one more polymerisable compounds and a liquid-crystalline component (B) containing one more compounds of the general formula I and/or IA in which R0, X0 and L1-6 have the meanings indicated in Claim 1, and to the use thereof in electro-optical liquid-crystal displays.
    Type: Application
    Filed: August 8, 2012
    Publication date: February 14, 2013
    Applicant: MERCK PATENT GESELLSCHAFT MIT BESCHRANKTER HAFTUNG
    Inventors: Gavin HUNG, Roger CHANG, Kris TSAI, Glavin OYANG
  • Patent number: 7892412
    Abstract: A manufacturing process of an embedded type flexible or rigid printed circuit board includes multiple steps. First, a layer of dry film is applied to a layer of copper foil. Then a circuit pattern is formed on the copper foil through photolithography processes. An etching stop layer is electroplated on the copper foil according to the circuit pattern. The etching stop layer is then electroplated with copper. The copper foil is softened by a high temperature process after removing the dry film. Then the layer of the copper foil is etched after coating with an organic layer and the organic layer is solidified.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: February 22, 2011
    Assignee: Mutual-Tek Industries Co., Ltd.
    Inventor: Roger Chang
  • Patent number: 7844892
    Abstract: The invention provides improved mechanisms for the construction and rendering of graphical results sets for business intelligence reports derived from large volumes of data. This is achieved by various means including, determining the amount of useful data that can be rendered within the available display space while still being legible, determining the most effective way of displaying that data within the display space, and providing for limited control of the format and quantity of data displayed.
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: November 30, 2010
    Assignee: International Business Machines Corporation
    Inventors: Nadia Shewchenko, Henning Hoffmann, Roger Chang, Lesley Grignon
  • Patent number: 7603771
    Abstract: A method of providing at least two multilayer circuit boards, combining the at least two multilayer circuit boards to form a combined multilayer circuit board, and forming multiple outer conductive vias, circuits and contacts on the combined multilayer circuit board. Each multilayer circuit board is fabricated by the steps of preparing a single-layer printed circuit board having multiple chip sections, attaching at least one chip to the corresponding chip section, attaching a frame having multiple enclosures to the single-layer printed circuit board, attaching a semi-fluid glue sheet to the frame, vacuum pressing a conductive layer on the semi-fluid glue sheet and forming multiple conductive inner vias through the multilayer circuit board. The at least two multilayer circuit boards are combined by steps of reversing one of the multilayer circuit boards and vacuum pressing other multilayer circuit boards on the reversed multilayer circuit board.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: October 20, 2009
    Assignee: Mutual-Tek Industries Co., Ltd.
    Inventor: Roger Chang
  • Patent number: 7505282
    Abstract: A multilayer circuit board has a bottom and an upper multilayer circuit boards, a glue layer, multiple outer contact vias and two insulating lacquer layers. The bottom and the upper multilayer circuit boards respectively have multiple conductive wires, an insulating layer, a frame, multiple chips, a press laminate, a patterned conductive layer and at least one inner contact via. The glue layer sticks the bottom and the upper multilayer circuit boards together. The multiple contact vias are formed through the bottom and the upper multilayer circuit boards to electronically interconnect the conductive wires and the patterned conductive layers in the bottom and the upper multilayer circuit boards. The insulating lacquer layers are respectively coated under and on portions of the patterned conductive layers in the bottom and the upper multilayer circuit boards to protect the patterned conductive layers, wherein the un-coated patterned conductive layers become multiple contacts.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: March 17, 2009
    Assignee: Mutual-TEK Industries Co., Ltd.
    Inventor: Roger Chang
  • Publication number: 20090056118
    Abstract: A method has acts of providing at least two multilayer circuit boards, combining the at least two multilayer circuit boards to form a combined multilayer circuit board, forming multiple outer conductive vias, circuits and contacts on the combined multilayer circuit board. Each multilayer circuit board is fabricated by steps of preparing a single-layer printed circuit board having multiple chip sections, attaching at least one chip to the corresponding chip section, attaching a frame having multiple enclosures to the single-layer printed circuit board, attaching a semi-fluid glue sheet to the frame, vacuum pressing a conductive layer on the semi-fluid glue sheet and forming multiple conductive inner vias through the multilayer circuit board. The at least two multilayer circuit boards are combined by steps of reversing one of the multilayer circuit boards and vacuum pressing other multilayer circuit boards on the reversed multilayer circuit board.
    Type: Application
    Filed: October 31, 2008
    Publication date: March 5, 2009
    Inventor: Roger CHANG
  • Publication number: 20080101044
    Abstract: A multilayer circuit board has a bottom and an upper multilayer circuit boards, a glue layer, multiple outer contact vias and two insulating lacquer layers. The bottom and the upper multilayer circuit boards respectively have multiple conductive wires, an insulating layer, a frame, multiple chips, a press laminate, a patterned conductive layer and at least one inner contact via. The glue layer sticks the bottom and the upper multilayer circuit boards together. The multiple contact vias are formed through the bottom and the upper multilayer circuit boards to electronically interconnect the conductive wires and the patterned conductive layers in the bottom and the upper multilayer circuit boards. The insulating lacquer layers are respectively coated under and on portions of the patterned conductive layers in the bottom and the upper multilayer circuit boards to protect the patterned conductive layers, wherein the un-coated patterned conductive layers become multiple contacts.
    Type: Application
    Filed: October 31, 2006
    Publication date: May 1, 2008
    Inventor: Roger Chang
  • Publication number: 20080057627
    Abstract: A method has acts of providing at least two multilayer circuit boards, combining the at least two multilayer circuit boards to form a combined multilayer circuit board, forming multiple outer conductive vias, circuits and contacts on the combined multilayer circuit board. Each multilayer circuit board is fabricated by steps of preparing a single-layer printed circuit board having multiple chip sections, attaching at least one chip to the corresponding chip section, attaching a frame having multiple enclosures to the single-layer printed circuit board, attaching a semi-fluid glue sheet to the frame, vacuum pressing a conductive layer on the semi-fluid glue sheet and forming multiple conductive inner vias through the multilayer circuit board. The at least two multilayer circuit boards are combined by steps of reversing one of the multilayer circuit boards and vacuum pressing other multilayer circuit boards on the reversed multilayer circuit board.
    Type: Application
    Filed: August 29, 2006
    Publication date: March 6, 2008
    Inventor: Roger Chang
  • Publication number: 20080046805
    Abstract: The invention provides improved mechanisms for the construction and rendering of graphical results sets for business intelligence reports derived from large volumes of data. This is achieved by various means including, determining the amount of useful data that can be rendered within the available display space while still being legible, determining the most effective way of displaying that data within the display space, and providing for limited control of the format and quantity of data displayed.
    Type: Application
    Filed: August 17, 2006
    Publication date: February 21, 2008
    Applicant: Cognos Incorporated
    Inventors: Nadia Shewchenko, Henning Hoffmann, Roger Chang, Lesley Grignon
  • Publication number: 20070295606
    Abstract: A manufacturing process of an embedded type flexible or rigid printed circuit board includes multiple steps. First, a layer of dry film is applied to a layer of copper foil. Then a circuit pattern is formed on the copper foil through photolithography processes. An etching stop layer is electroplated on the copper foil according to the circuit pattern. The etching stop layer is then electroplated with copper. The copper foil is softened by a high temperature process after removing the dry film. Then the layer of the copper foil is etched after coating with an organic layer and the organic layer is solidified.
    Type: Application
    Filed: September 6, 2007
    Publication date: December 27, 2007
    Applicant: MUTUAL-TEK INDUSTRIES CO., LTD.
    Inventor: Roger Chang