Abstract: At a high-level, a novel pricing technique is dependent in part on the influence of followers or friends on one or more internet social site that a user has.

Abstract: Data may be transferred from a communication subsystem of a first device to a communication subsystem of a second device contactlessly, at high speed, and without intervention by host processors of either device. Devices may be programmed or personalized at the factory or warehouse, and may personalized at a warehouse or at a point of sale while in the box. Various modes of operation and use scenarios are described. Portions of the devices themselves, or a transmission path between the devices may be shielded against snooping by a material which degrades an EHF signal passing therethrough.

Abstract: Embodiments of the invention are generally directed to a hybrid interface for serial and parallel communication. An embodiment of a method includes initializing a first apparatus for transmission of data to or reception of data from a second apparatus, switching an interface for the first apparatus to a first mode for a parallel interface, the parallel interface including a first plurality of pins, and transmitting or receiving parallel data in the first mode via the first plurality of pins. The method further includes switching the interface of the first apparatus to a second mode for a serial interface, the serial interface including a second plurality of pins, the first plurality of pins and the second plurality of pins both including an overlapping set of pins, and transmitting or receiving serial data in the second mode via the second plurality of pins.

Abstract: Embodiments of the invention are generally directed to a hybrid interface for serial and parallel communication. An embodiment of a method includes initializing a first apparatus for transmission of data to or reception of data from a second apparatus, switching an interface for the first apparatus to a first mode for a parallel interface, the parallel interface including a first plurality of pins, and transmitting or receiving parallel data in the first mode via the first plurality of pins. The method further includes switching the interface of the first apparatus to a second mode for a serial interface, the serial interface including a second plurality of pins, the first plurality of pins and the second plurality of pins both including an overlapping set of pins, and transmitting or receiving serial data in the second mode via the second plurality of pins.

Abstract: A prefetch unit for use with a cache subsystem. The prefetch unit includes a stream storage coupled to a prefetch unit. The stream storage may include a plurality of locations configured to store a plurality of entries each corresponding to a respective range of prefetch addresses. The prefetch control may be configured to prefetch an address in response to receiving a cache access request including an address that is within the respective range of prefetch addresses of any of the plurality of entries.

Abstract: A system and method for managing a memory system. A system includes a plurality of processing entities and a cache which is shared by the processing entities. Responsive to a replacement event, circuitry may identify data entries of the shared cache which are candidates for replacement. Data entries which have been identified as candidates for replacement may be removed as candidates for replacement in response to detecting the data entry corresponds to data which is shared by at least two of the plurality of processing entities. The circuitry may maintain an indication as to which of the processing entities caused an initial allocation of data into the shared cache. When the circuitry detects that a particular data item is accessed by a processing entity other than a processing entity which caused an allocation of the given data item, the data item may be deemed classified as shared data.

Abstract: A system and method for managing a cache subsystem. A system comprises a plurality of processing entities, a cache shared by the plurality of processing entities, and circuitry configured to manage allocations of data into the cache. Cache controller circuitry is configured to allocate data in the cache at a less favorable position in the replacement stack in response to determining a processing entity which corresponds to the allocated data has relatively poor cache behavior compared to other processing entities. The circuitry is configured to track a relative hit rate for each processing entity, such as a thread or processor core. A figure of merit may be determined for each processing entity which reflects how well a corresponding processing entity is behaving with respect to the cache. Processing entities which have a relatively low figure of merit may have their data allocated in the shared cache at a lower level in the cache replacement stack.

Abstract: A cache memory subsystem including a fixed latency read/write pipeline. The cache memory subsystem includes a cache storage which may be configured to store a plurality of cache lines of data. The cache memory subsystem further includes a scheduler which may be configured to schedule reads and writes of information associated with the cache storage using a fixed latency pipeline. In response to scheduling a read request, the scheduler may be further configured to cause an associated write to occur a fixed number of cycles after the scheduling of the read request.

Abstract: A cache memory system including a cache memory employing a tag including associated touch bits. The system includes a first cache memory subsystem having a first cache storage and a second cache memory subsystem including a second cache storage. The first cache storage may store a first plurality of cache lines of data. The second cache storage may store a second plurality of cache lines of data. Further the second cache memory subsystem includes a tag storage which may store a plurality of tags each corresponding to a respective cache line of the second plurality of cache lines. In addition, each of said plurality of tags includes an associated bit indicative of whether a copy of the corresponding respective cache line is stored within the first cache memory subsystem.

Abstract: A prefetch mechanism includes a prefetch predictor table coupled to a prefetch control. The prefetch predictor table may include a plurality of locations configured to store a plurality of entries each indicative of a stride between a respective pair of memory requests. Each of the plurality of entries may be stored in a respective one of the plurality of locations dependent upon a value of an earlier stride. The prefetch control may be configured to prefetch an address based upon a given one of the plurality of entries in the prefetch predictor table.