Patents by Inventor Roger Panicacci

Roger Panicacci has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210136274
    Abstract: An image sensor system may include an array of image sensor pixels. A portion of the image sensor array that includes high dynamic range (HDR) content may be oversampled at a higher rate than the rest of the array to generate multiple sub-frames. When reading out the multiple sub-frames, the charge transfer gate pulse may only be partially asserted so that only a part of the full well charge is drained. Partially asserting the charge transfer gate pulse allows drainage of the high light signals without perturbing the low light signals. The last sub-frame should be read out by fully asserting the charge transfer gate pulse to ensure than the entire well charge is drained. Data collected from the multiple sub-frames may be accumulated using digital accumulation circuitry. The rest of the array can be read out at the nominal frame rate.
    Type: Application
    Filed: November 1, 2019
    Publication date: May 6, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Roger PANICACCI
  • Publication number: 20210075986
    Abstract: Imaging circuitry may include an array of pixels for capturing an image. A subset of the pixels in the array may be selected to perform depth sensing using region of interest (ROI) switching circuitry incorporated within an intermediate die that is stacked between a top image sensor die in which the array of pixels are formed and a bottom digital processing die. The imaging circuitry may be further provided with depth sensing circuitry having a current memory circuit, a current integrator circuit, a time-to-digital converter, and a loading circuit to compute a time of flight for a laser pulse by sensing changes in the pixel source follower gate current. Such depth sensing schemes may be applied to sense horizontally-oriented features, vertically-oriented features, diagonally-oriented features, or irregularly shaped features.
    Type: Application
    Filed: July 15, 2020
    Publication date: March 11, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Roger PANICACCI
  • Publication number: 20210058580
    Abstract: Imaging circuitry may include circuits for implementing feature extraction. The imaging circuitry may include pixels configured to generate pixel values. The pixel values may be optionally scaled by kernel weighting factors. The pixels may be coupled together via a source follower drain path, and a source follower gate in one of the pixels may be selected for readout by coupling that source follower gate to an integrator circuit to compute a feature result. Multiple feature results may be computed successively to detect an event change in either the digital domain or the analog domain. Such feature detection schemes may be applied to detect horizontally-oriented features, vertically-oriented features, diagonally-oriented features, or irregularly shaped features.
    Type: Application
    Filed: May 19, 2020
    Publication date: February 25, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Roger PANICACCI
  • Publication number: 20210051284
    Abstract: Imaging circuitry may include circuits for implementing charge mode feature extraction in the analog domain. The imaging circuitry may include pixels configured to generate pixel values. The pixel values may then be weighted using adjustable weighting circuits to generate corresponding weighted pixel values. The weighted pixels values may then be combined to obtain an output neuron voltage for at least one layer in a neural network. The output neuron voltage may be stored in idle pixels, may be combined with other weighted pixel values, and may be otherwise manipulated prior to being processed in the digital domain. Performing feature extraction in the analog domain for each layer of results in the neural network saves power and area by avoiding the need to move data around to conventional digital memories.
    Type: Application
    Filed: March 17, 2020
    Publication date: February 18, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Roger PANICACCI, Tomas GEURTS
  • Publication number: 20210051290
    Abstract: Imaging circuitry may include circuits for implementing feature extraction in the analog domain. The imaging circuitry may include pixels configured to generate pixel values. The pixel values may then be weighted using variable charge integration times, variable resistors in the readout path, and/or variable switch on times in the readout path. The weighted pixels values may be binned and combined to obtain an output neuron voltage for at least one layer in a neural network. Performing feature extraction in the analog domain for each layer of results in the neural network saves power and area by avoiding the need to move data around to conventional digital memories.
    Type: Application
    Filed: April 21, 2020
    Publication date: February 18, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Roger PANICACCI, Tim W. CHAN
  • Publication number: 20210051287
    Abstract: Imaging circuitry may include circuits for implementing current or voltage mode feature extraction in the analog domain. The imaging circuitry may include pixels configured to generate pixel values. The pixel values may then be weighted using adjustable weighting circuits to generate corresponding weighted pixel values. The adjustable weighting circuits may be selectively coupled to the floating diffusion node in each pixel. The weighted pixels values may then be combined to obtain an output neuron voltage for at least one layer in a neural network. Performing feature extraction in the analog domain for each layer of results in the neural network saves power and area by avoiding the need to move data around to conventional digital memories.
    Type: Application
    Filed: March 24, 2020
    Publication date: February 18, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Roger PANICACCI, Tim CHAN
  • Patent number: 10859434
    Abstract: An image sensor may include an array of image pixels coupled to analog-to-digital conversion circuitry formed from pinned photodiode charge transfer circuits. Majority charge carriers for the pinned photodiodes in the charge transfer circuits may be electrons for photodiode wells formed from n-type doped regions and may be holes for photodiode formed from p-type doped regions. Pinned photodiodes may be used for charge integration onto a capacitive circuit node. Pinned photodiodes may also be used for charge subtraction from a capacitive circuit node. Comparator circuitry may be used to determine digital values for the pixel output levels in accordance with single-slope conversion, successive-approximation-register conversion, cyclic conversion, and first or second order delta-sigma conversion techniques. The array of image pixels used for imaging may have a conversion mode wherein at least a portion of the pixel circuitry in the array are operated similar to the charge transfer circuits.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: December 8, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Roger Panicacci
  • Patent number: 10249656
    Abstract: An image sensor may include an array of image pixels coupled to analog-to-digital conversion circuitry formed from pinned photodiode charge transfer circuits. Majority charge carriers for the pinned photodiodes in the charge transfer circuits may be electrons for photodiode wells formed from n-type doped regions and may be holes for photodiode formed from p-type doped regions. Pinned photodiodes may be used for charge integration onto a capacitive circuit node. Pinned photodiodes may also be used for charge subtraction from a capacitive circuit node. Comparator circuitry may be used to determine digital values for the pixel output levels in accordance with single-slope conversion, successive-approximation-register conversion, cyclic conversion, and first or second order delta-sigma conversion techniques. The array of image pixels used for imaging may have a conversion mode wherein at least a portion of the pixel circuitry in the array are operated similar to the charge transfer circuits.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: April 2, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Roger Panicacci
  • Patent number: 10192922
    Abstract: An image sensor may include an array of image pixels coupled to analog-to-digital conversion circuitry formed from pinned photodiode charge transfer circuits. Majority charge carriers for the pinned photodiodes in the charge transfer circuits may be electrons for photodiode wells formed from n-type doped regions and may be holes for photodiode formed from p-type doped regions. Pinned photodiodes may be used for charge integration onto a capacitive circuit node. Pinned photodiodes may also be used for charge subtraction from a capacitive circuit node. Comparator circuitry may be used to determine digital values for the pixel output levels in accordance with single-slope conversion, successive-approximation-register conversion, cyclic conversion, and first or second order delta-sigma conversion techniques. The array of image pixels used for imaging may have a conversion mode wherein at least a portion of the pixel circuitry in the array are operated similar to the charge transfer circuits.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: January 29, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Roger Panicacci
  • Publication number: 20180274975
    Abstract: An image sensor may include an array of image pixels coupled to analog-to-digital conversion circuitry formed from pinned photodiode charge transfer circuits. Majority charge carriers for the pinned photodiodes in the charge transfer circuits may be electrons for photodiode wells formed from n-type doped regions and may be holes for photodiode formed from p-type doped regions. Pinned photodiodes may be used for charge integration onto a capacitive circuit node. Pinned photodiodes may also be used for charge subtraction from a capacitive circuit node. Comparator circuitry may be used to determine digital values for the pixel output levels in accordance with single-slope conversion, successive-approximation-register conversion, cyclic conversion, and first or second order delta-sigma conversion techniques. The array of image pixels used for imaging may have a conversion mode wherein at least a portion of the pixel circuitry in the array are operated similar to the charge transfer circuits.
    Type: Application
    Filed: May 30, 2018
    Publication date: September 27, 2018
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Roger PANICACCI
  • Patent number: 10001406
    Abstract: An image sensor may include an array of image pixels coupled to analog-to-digital conversion circuitry formed from pinned photodiode charge transfer circuits. Majority charge carriers for the pinned photodiodes in the charge transfer circuits may be electrons for photodiode wells formed from n-type doped regions and may be holes for photodiode formed from p-type doped regions. Pinned photodiodes may be used for charge integration onto a capacitive circuit node. Pinned photodiodes may also be used for charge subtraction from a capacitive circuit node. Comparator circuitry may be used to determine digital values for the pixel output levels in accordance with single-slope conversion, successive-approximation-register conversion, cyclic conversion, and first or second order delta-sigma conversion techniques. The array of image pixels used for imaging may have a conversion mode wherein at least a portion of the pixel circuitry in the array are operated similar to the charge transfer circuits.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: June 19, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Roger Panicacci
  • Patent number: 9848141
    Abstract: An image sensor may include an array of image sensor pixels. Each image sensor pixel may have signal storage capabilities implemented through a write-back supply line and a control transistor for the supply line. Each image sensor pixel may output pixel values over column lines to switching circuitry. The switching circuitry may route the pixel values to signal processing circuitry. The signal processing circuitry may perform analog and/or digital processing operations utilizing analog circuits or pinned diode devices for image signal processing on the pixel values to output processed pixel values. The processing circuitry may send the processed pixel values back to the array. This allows the array to act as memory circuitry to support processing operations on processing circuitry in close proximity to the array. Configured this way, signal processing can be performed in close proximity to the array without having to move pixel signals to peripheral processing circuitry.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: December 19, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Roger Panicacci, Marko Mlinar
  • Publication number: 20170350756
    Abstract: An image sensor may include an array of image pixels coupled to analog-to-digital conversion circuitry formed from pinned photodiode charge transfer circuits. Majority charge carriers for the pinned photodiodes in the charge transfer circuits may be electrons for photodiode wells formed from n-type doped regions and may be holes for photodiode formed from p-type doped regions. Pinned photodiodes may be used for charge integration onto a capacitive circuit node. Pinned photodiodes may also be used for charge subtraction from a capacitive circuit node. Comparator circuitry may be used to determine digital values for the pixel output levels in accordance with single-slope conversion, successive-approximation-register conversion, cyclic conversion, and first or second order delta-sigma conversion techniques. The array of image pixels used for imaging may have a conversion mode wherein at least a portion of the pixel circuitry in the array are operated similar to the charge transfer circuits.
    Type: Application
    Filed: June 7, 2016
    Publication date: December 7, 2017
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Roger PANICACCI
  • Publication number: 20170352696
    Abstract: An image sensor may include an array of image pixels coupled to analog-to-digital conversion circuitry formed from pinned photodiode charge transfer circuits. Majority charge carriers for the pinned photodiodes in the charge transfer circuits may be electrons for photodiode wells formed from n-type doped regions and may be holes for photodiode formed from p-type doped regions. Pinned photodiodes may be used for charge integration onto a capacitive circuit node. Pinned photodiodes may also be used for charge subtraction from a capacitive circuit node. Comparator circuitry may be used to determine digital values for the pixel output levels in accordance with single-slope conversion, successive-approximation-register conversion, cyclic conversion, and first or second order delta-sigma conversion techniques. The array of image pixels used for imaging may have a conversion mode wherein at least a portion of the pixel circuitry in the array are operated similar to the charge transfer circuits.
    Type: Application
    Filed: June 7, 2016
    Publication date: December 7, 2017
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Roger PANICACCI
  • Publication number: 20170352694
    Abstract: An image sensor may include an array of image pixels coupled to analog-to-digital conversion circuitry formed from pinned photodiode charge transfer circuits. Majority charge carriers for the pinned photodiodes in the charge transfer circuits may be electrons for photodiode wells formed from n-type doped regions and may be holes for photodiode formed from p-type doped regions. Pinned photodiodes may be used for charge integration onto a capacitive circuit node. Pinned photodiodes may also be used for charge subtraction from a capacitive circuit node. Comparator circuitry may be used to determine digital values for the pixel output levels in accordance with single-slope conversion, successive-approximation-register conversion, cyclic conversion, and first or second order delta-sigma conversion techniques. The array of image pixels used for imaging may have a conversion mode wherein at least a portion of the pixel circuitry in the array are operated similar to the charge transfer circuits.
    Type: Application
    Filed: June 7, 2016
    Publication date: December 7, 2017
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Roger PANICACCI
  • Publication number: 20170332023
    Abstract: An image sensor may include an array of image sensor pixels. Each image sensor pixel may have signal storage capabilities implemented through a write-back supply line and a control transistor for the supply line. Each image sensor pixel may output pixel values over column lines to switching circuitry. The switching circuitry may route the pixel values to signal processing circuitry. The signal processing circuitry may perform analog and/or digital processing operations utilizing analog circuits or pinned diode devices for image signal processing on the pixel values to output processed pixel values. The processing circuitry may send the processed pixel values back to the array. This allows the array to act as memory circuitry to support processing operations on processing circuitry in close proximity to the array. Configured this way, signal processing can be performed in close proximity to the array without having to move pixel signals to peripheral processing circuitry.
    Type: Application
    Filed: May 10, 2016
    Publication date: November 16, 2017
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Roger PANICACCI, Marko MLINAR
  • Patent number: 9648265
    Abstract: An image sensor may have an array of pixels and readout circuitry. The array may include image pixels that generate signals in response to image light and reference pixels that generate signals in response to electrical noise. The readout circuitry may obtain first pixel values from the image pixels and may obtain second pixel values from the reference pixels. The readout circuitry may generate an extended precision pixel value based on the second pixel values that have an extended bit width relative to the each of the second pixel values. The readout circuitry may generate multiple dithered correction values by adding randomized sequences of least significant bits to the extended precision pixel value. The readout circuitry may mitigate visible quantization error and noise such as row-correlated and column-correlated noise in the final image by subtracting the dithered correction values from corresponding first pixel values.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: May 9, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Roger Panicacci, Jeffery Beck, Barry Vanhoff
  • Patent number: 9554071
    Abstract: An imaging device that stores charge from a photosensor under at least one storage gate. A driver used to operate the at least one storage gate, senses how much charge was transferred to the storage gate. The sensed charge is used to obtain at least one signature of the image scene. The at least one signature may then be used for processing such as e.g., motion detection, auto-exposure, and auto-white balancing.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: January 24, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Roger Panicacci
  • Publication number: 20150312499
    Abstract: An image sensor may have an array of pixels and readout circuitry. The array may include image pixels that generate signals in response to image light and reference pixels that generate signals in response to electrical noise. The readout circuitry may obtain first pixel values from the image pixels and may obtain second pixel values from the reference pixels. The readout circuitry may generate an extended precision pixel value based on the second pixel values that have an extended bit width relative to the each of the second pixel values. The readout circuitry may generate multiple dithered correction values by adding randomized sequences of least significant bits to the extended precision pixel value. The readout circuitry may mitigate visible quantization error and noise such as row-correlated and column-correlated noise in the final image by subtracting the dithered correction values from corresponding first pixel values.
    Type: Application
    Filed: April 29, 2014
    Publication date: October 29, 2015
    Inventors: Roger Panicacci, Jeffery Beck, Barry Vanhoff
  • Patent number: 8908071
    Abstract: Methods, apparatus and systems may operate to copy pixel charge, compensating for image subject shift within in an imaging array during exposure time of an imaging device. Activities may include transferring charge from one or more source pixels to one or more buffer pixels within the same pixel array, and copying the charge to destination pixels within the same pixel array prior to an end of the image integration time. Charge transfer may include transfer of charge from more than one array on a single die. Additional activities may include transferring charge from one or more source pixels to one or more destination pixels multiple times prior to the end of the image integration time.
    Type: Grant
    Filed: May 14, 2014
    Date of Patent: December 9, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Roger Panicacci