Patents by Inventor Roger R. Lee
Roger R. Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240081478Abstract: A sole structure for an article of footwear includes a chassis and a cushioning arrangement. The chassis includes a recess formed between a first surface and a second surface facing the first surface. The cushioning arrangement includes a first cushioning element protruding from the first surface and including a first plurality of lobes and a second cushioning element protruding from the second surface and including a second plurality of lobes contacting the first plurality of lobes. At least one of the first cushioning element and the second cushioning element may include a fluid-filled bladder. A first side of each cushioning element includes a substantially planar base and a second side of each cushioning element includes the lobes formed on an opposite side from the base. The base of each cushioning element is attached to a respective one of the surfaces of the recess.Type: ApplicationFiled: November 24, 2023Publication date: March 14, 2024Applicant: NIKE, Inc.Inventors: Fidencio Campos, II, Zachary M. Elder, Jordyn Klumpp, Eric Y. Lee, Fiona L. Lesecq, Damian R. Manspeaker, Roger Paul Murphy, Sebastian Tesche
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Patent number: 8124491Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location.Type: GrantFiled: August 25, 2009Date of Patent: February 28, 2012Assignee: Micron Technology, Inc.Inventors: D. Mark Durcan, Trung T. Doan, Roger R. Lee, Fernando Gonzalez
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Publication number: 20090311843Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location.Type: ApplicationFiled: August 25, 2009Publication date: December 17, 2009Inventors: D. Mark Durcan, Trung T. Doan, Roger R. Lee, Fernando Gonzalez, Er-Xuan Ping
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Patent number: 7625795Abstract: Container capacitor structure and method of construction. An etch mask and etch are used to expose portions of an exterior surface of an electrode (“bottom electrodes”) of the structure. The etch provides a recess between proximal pairs of container capacitor structures, which is available for forming additional capacitance. A capacitor dielectric and top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Surface area common to both the first electrode and second electrodes is increased over using only the interior surface, providing additional capacitance without decreasing spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.Type: GrantFiled: September 1, 2005Date of Patent: December 1, 2009Assignee: Micron Technology, Inc.Inventors: D. Mark Durcan, Trung T. Doan, Roger R. Lee, Fernando Gonzalez, Er-Xuan Ping
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Patent number: 7579235Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location.Type: GrantFiled: October 10, 2006Date of Patent: August 25, 2009Assignee: Micron Technology, Inc.Inventors: D. Mark Durcan, Trung T. Doan, Roger R. Lee, Fernando Gonzalez, Er-Xuan Ping
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Patent number: 7192829Abstract: Floating gate transistors and methods of forming the same are described. In one implementation, a floating gate is formed over a substrate. The floating gate has an inner first portion and an outer second portion. Conductivity enhancing impurity is provided in the inner first portion to a greater concentration than conductivity enhancing impurity in the outer second portion. In another implementation, the floating gate is formed from a first layer of conductively doped semiconductive material and a second layer of substantially undoped semiconductive material. In another implementation, the floating gate is formed from a first material having a first average grain size and a second material having a second average grain size which is larger than the first average grain size.Type: GrantFiled: July 17, 1998Date of Patent: March 20, 2007Assignee: Micron Technology, Inc.Inventors: J. Dennis Keller, Roger R. Lee
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Patent number: 7160785Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location.Type: GrantFiled: August 31, 2000Date of Patent: January 9, 2007Assignee: Micron Technology, Inc.Inventors: D. Mark Durcan, Trung T. Doan, Roger R. Lee, Fernando Gonzalez
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Patent number: 6791141Abstract: Floating gate transistors and methods of forming the same are described. In one implementation, a floating gate is formed over a substrate. The floating gate has an inner first portion and an outer second portion. Conductivity enhancing impurity is provided in the inner first portion to a greater concentration than conductivity enhancing impurity in the outer second portion. In another implementation, the floating gate is formed from a first layer of conductively doped semiconductive material and a second layer of substantially undoped semiconductive material. In another implementation, the floating gate is formed from a first material having a first average grain size and a second material having a second average grain size which is larger than the first average grain size.Type: GrantFiled: October 13, 1998Date of Patent: September 14, 2004Assignee: Micron Technology, Inc.Inventors: J. Dennis Keller, Roger R. Lee
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Patent number: 6753565Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location.Type: GrantFiled: August 31, 2000Date of Patent: June 22, 2004Assignee: Micron Technology, Inc.Inventors: D. Mark Durcan, Trung T. Doan, Roger R. Lee, Fernando Gonzalez
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Patent number: 6693319Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location.Type: GrantFiled: August 31, 2000Date of Patent: February 17, 2004Assignee: Micron Technology, Inc.Inventors: D. Mark Durcan, Trung T. Doan, Roger R. Lee, Fernando Gonzalez
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Patent number: 6661051Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location.Type: GrantFiled: August 31, 2000Date of Patent: December 9, 2003Assignee: Micron Technology, Inc.Inventors: D. Mark Durcan, Trung T. Doan, Roger R. Lee, Fernando Gonzalez
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Patent number: 6620680Abstract: Method for forming at least a portion of a top electrode of a container capacitor and at least a portion of a contact plug in one deposition are described. In one embodiment, the top electrode is formed interior to a bottom electrode of the container capacitor. In another embodiment, the top electrode is formed interior to, and exterior and below a portion of the bottom electrode of the container capacitor. The method of forming a top electrode of a container capacitor and a contact plug with a same deposition is particularly well-suited for high-density memory array formation.Type: GrantFiled: February 22, 2002Date of Patent: September 16, 2003Assignee: Micron Technology, Inc.Inventors: D. Mark Durcan, Trung T. Doan, Roger R. Lee, Fernando Gonzalez
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Patent number: 6608342Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location.Type: GrantFiled: August 31, 2000Date of Patent: August 19, 2003Assignee: Micron Technology, Inc.Inventors: D. Mark Durcan, Trung T. Doan, Roger R. Lee, Fernando Gonzalez, Er-Xuan Ping
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Patent number: 6528834Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location.Type: GrantFiled: August 31, 2000Date of Patent: March 4, 2003Assignee: Micron Technology, Inc.Inventors: D. Mark Durcan, Trung T. Doan, Roger R. Lee, Fernando Gonzalez
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Publication number: 20020125508Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location.Type: ApplicationFiled: May 3, 2002Publication date: September 12, 2002Applicant: Micron Technology, Inc.Inventors: D. Mark Durcan, Trung T. Doan, Roger R. Lee, Fernando Gonzalez, Er-Xuan Ping
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Publication number: 20020098654Abstract: Method for forming at least a portion of a top electrode of a container capacitor and at least a portion of a contact plug in one deposition are described. In one embodiment, the top electrode is formed interior to a bottom electrode of the container capacitor. In another embodiment, the top electrode is formed interior to, and exterior and below a portion of the bottom electrode of the container capacitor. The method of forming a top electrode of a container capacitor and a contact plug with a same deposition is particularly well-suited for high-density memory array formation.Type: ApplicationFiled: February 22, 2002Publication date: July 25, 2002Applicant: Micron Technology, Inc.Inventors: D. Mark Durcan, Trung T. Doan, Roger R. Lee, Fernando Gonzalez
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Patent number: 6395600Abstract: Method for forming at least a portion of a top electrode of a container capacitor and at least a portion of a contact plug in one deposition are described. In one embodiment, the top electrode is formed interior to a bottom electrode of the container capacitor. In another embodiment, the top electrode is formed interior to, and exterior and below a portion of the bottom electrode of the container capacitor. The method of forming a top electrode of a container capacitor and a contact plug with a same deposition is particularly well-suited for high-density memory array formation.Type: GrantFiled: September 2, 1999Date of Patent: May 28, 2002Assignee: Micron Technology, Inc.Inventors: D. Mark Durcan, Trung T. Doan, Roger R. Lee, Fernando Gonzalez
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Patent number: 6391735Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location.Type: GrantFiled: August 31, 2000Date of Patent: May 21, 2002Assignee: Micron Technology, Inc.Inventors: D. Mark Durcan, Trung T. Doan, Roger R. Lee, Fernando Gonzalez
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Patent number: 6333240Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location.Type: GrantFiled: August 31, 2000Date of Patent: December 25, 2001Assignee: Micron Technology, Inc.Inventors: D. Mark Durcan, Trung T. Doan, Roger R. Lee, Fernando Gonzalez
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Patent number: 6329263Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location.Type: GrantFiled: August 31, 2000Date of Patent: December 11, 2001Assignee: Micron Technology, Inc.Inventors: D. Mark Durcan, Trung T. Doan, Roger R. Lee, Fernando Gonzalez, Er-Xuan Ping