Abstract: The present invention introduces a process to fabricate very low resistive antifuse elements by introducing Antimony (Sb) into one or both of the antifuse element's electrodes and thereby resulting in said very low resistive (programmed) antifuse element. Introducing Sb into the antifuse electrode(s) reduces the depletion width of the dopant impurities thereby causing a large concentration of n+ dopants in the antifuse electrode(s). This allows a reduction in the voltage required across the electrodes to breakdown the inner lying dielectric and thus program or short the electrodes together. In addition, once the two electrodes become shorted together to form a filament, the Sb will flow form one or both electrode(s) and thereby heavily dope the filament itself with n+ atoms. With the presence of the heavy concentration of n+ atoms in the filament, the shorted antifuse element is reduced in resistance by as much as a few hundred ohms or below when compared to antifuse elements fabricated by other methods.

Abstract: An array of finned memory cell capacitors on a semiconductor substrate includes: a) an array of electrically insulated word lines atop a semiconductor substrate; b) first and second active regions adjacent the word lines; c) capacitor storage nodes electrically connecting with the first active regions, individual capacitor storage nodes including: i) a layer of first conductive material conductively connecting with a first active region, the layer of first conductive material having opposed outer lateral edges, and ii) a layer of conductively doped storage node polysilicon overlying and conductively connecting with the layer of first conductive material, the storage node polysilicon projecting laterally outward beyond the outer lateral edges of the first conductive material to define opposing storage node capacitor fins projecting laterally above adjacent word lines; d) a layer of capacitor dielectric electrically connecting with the storage node capacitor fins; e) a layer of electrically conductive cell poly

Abstract: A PROM cell allows improved, lower voltage programming and reduced leakage of the charge from the floating gate to the substrate (channel) region. The inventive cell uses a thin gate oxide layer along with a floating gate which is lightly doped except on one edge. This edge, for example near the drain region, is heavily doped with an angled implant. The thin gate oxide functions as thick oxide under the lightly doped region, thereby preventing the leakage and high coupling between the substrate and floating gate of a conventional thin oxide layer. The thin oxide under the heavily doped areas of the floating gate functions as thin oxide, thereby allowing improved, lower voltage programming.

Abstract: The present invention provides a programmable structure for programmable integrated circuits, such as programmable read-only memory (PROM) which utilizes one-sided ozone spacers constructed on the digitlines as well as on the wordlines thereby providing two, one time programmable nodes at each digit/word/digit' intersection. An oxide/nitride/oxide layer (ONO) is used as an interface between underlying parallel rows of digit lines, having one-sided ozone spacers, and overlying parallel columns of word lines, also having one-sided ozone spacers, and further overlying parallel rows' of digitlines' in a programmable read only memory. With a lower level of digitlines passing under a middle level of wordlines and an upper level of digitlines' passing over the middle level of wordlines, a row/column/digit' matrix is formed thereby providing a programmable row/column/row' matrix in a memory array.

Abstract: A semiconductor processing method for forming a substrate isolation trench includes the following steps: a) providing a layer of selected material atop a substrate to a selected thickness; b) providing a sacrificial layer of a selected etch stop material to a selected thickness atop the layer of selected material; c) patterning and etching through the sacrificial layer and selected material layer, and into the substrate to define an isolation trench; d) depositing a trench filling material to a selected thickness atop the substrate and within and filling the isolation trench; e) planarize etching the trench filling material using the sacrificial layer as an effective etch stop for such planarize etching; f) etching the sacrificial layer from the substrate and thereby leaving a pillar of trench filling material projecting upwardly relative to an upper substrate surface; and g) selectively etching the projecting pillar relative to the upper substrate surface.

Abstract: The present invention provides improved programmability of antifuse elements by utilizing local enhancement of an underlying diffusion region. During an existing fabrication of a semiconductor device using antifuse elements after the access lines (usually word lines) are formed, a self-aligning trench is etched between two neighboring access lines thereby severing an underlying diffusion region. Following an etch back of the access lines' spacers a low energy, heavy dose implant dopes the exposed edges of the diffusion region resulting from the spacer etch back, as well as the bottom of the trench. An antifuse dielectric is formed followed by placing of a second conductive access line (usually the source lines) thus filling the trench to serve as the programmable antifuse element. The heavily doped areas in the diffusion region will now allow a reduction in programming voltage level, while providing a sufficient rupture of the antifuse dielectric.

Abstract: The present invention comprises a programmable structure for a integrated circuits, such as programmable read-only memory (PROM) or option selections/redundancy repair on dynamic random access memories (DRAMs), which utilizes both antifuse and fuse elements for multiple programming. Various combinations of anti-fuse and fuse elements (series or series-parallel combinations) will allow multiple programming of a given node in a particular circuit design to allow greater programming flexibility.

Abstract: The invention is a product and method for forming the same comprising a storage contact capacitor of a DRAM device wherein the storage node capacitor plate comprises first and second capacitor portions. The first portion is a self-aligned Tungsten and TiN core. In a first embodiment the second portion is a storage node polysilicon deposited and subjected to an insitu phosphorus diffusion doping. In a second embodiment the second portion comprises tungsten fingers formed elevationally and horizontally to overlie the tungsten and TiN core. Portions of TiN provide spacing between adjacent tungsten fingers. An upper polysilicon layer functions as the upper capacitor plate and is insulated from the lower capacitor plate by a dielectric layer.

Abstract: Disclosed is a process for fabricating a semiconductor wafer to form a memory array and peripheral area, where the array comprises nonvolatile memory devices employing floating gate transistors and the peripheral area comprises CMOS transistors. A first layer of conductive material is applied atop insulating layers. A dielectric layer is applied atop the first conductive layer for use in floating gate transistors within the array. The dielectric layer and first conductive material are etched from the peripheral area, leaving patterned dielectric material and first conductive material in the array. A second layer of conductive material is applied atop the wafer to cover the peripheral area and dielectric layer of the array. The conductive and dielectric materials of the array are patterned and etched separately from the patterning and etching of conductive material of each of the first and second conductivity type CMOS transistors of the peripheral area.

Abstract: A dynamic random access memory (DRAM) storage cell having a storage contact capacitor comprising a tungsten and TiN storage node capacitor plate and the method for fabricating the same. At least a portion of the storage node capacitor plate is formed vertically in the DRAM. The TiN is controllably etched to increase the area of the storage node capacitor plate. An upper poly layer functions as the cell plate and is insulated from the storage node capacitor plate by a dielectric layer.