Patents by Inventor Roger S. Krabbenhoft
Roger S. Krabbenhoft has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11968780Abstract: An electronic printed circuit board structure for mitigating conductive anodic filament growth. The structure includes at least two conductive layers and a dielectric layer sandwiched between the conductive layers. At least one hole extends through the dielectric layer, and a layer of nonconductive material covers the at least one hole, wherein the nonconductive material is glass-free. A conductive plate layer is disposed over the nonconductive material layer to form a via connection in the structure.Type: GrantFiled: June 2, 2022Date of Patent: April 23, 2024Assignee: International Business Machines CorporationInventors: Kyle Indukummar Giesen, Sarah K. Czaplewski-Campbell, Roger S. Krabbenhoft
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Publication number: 20240098882Abstract: An electronic component includes a first trace configured to transmit a first signal and a second trace configured to transmit a second signal. The electronic component further includes a layer of conductive material separated from the first and second traces by a layer of insulative material. The electronic component further includes a first vertical wall formed in direct contact with the layer of conductive material. The electronic component further includes a second vertical wall formed in direct contact with the layer of conductive material. The second vertical wall is separated from the first vertical wall by a void, and the void extends between the first trace and the second trace.Type: ApplicationFiled: September 20, 2022Publication date: March 21, 2024Inventors: Matthew Doyle, DAVID CLIFFORD LONG, Matteo Cocchini, Russell A. Budd, James Busby, Roger S. Krabbenhoft, Arthur J. Higby
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Publication number: 20230397331Abstract: An electronic printed circuit board structure for mitigating conductive anodic filament growth. The structure includes at least two conductive layers and a dielectric layer sandwiched between the conductive layers. At least one hole extends through the dielectric layer, and a layer of nonconductive material covers the at least one hole, wherein the nonconductive material is glass-free. A conductive plate layer is disposed over the nonconductive material layer to form a via connection in the structure.Type: ApplicationFiled: June 2, 2022Publication date: December 7, 2023Inventors: Kyle Indukummar Giesen, Sarah K. Czaplewski-Campbell, Roger S. Krabbenhoft
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Patent number: 10595416Abstract: A circuit apparatus includes a first circuit feature upon a first insulator and a second circuit feature upon the first insulator. The first circuit feature includes a planarized surface and the second circuit feature includes an irregular surface. The first circuit feature and the second circuit feature may be formed from patterning a conductive sheet that is upon the first insulator. The conductive sheet includes an irregular surface and a planarized surface. Conductive sheet roughness is minimized in first regions thereof and is maintained in second regions thereof. Selectively planarizing portions of the conductive sheet allows for the utilization of lower cost rougher conductive sheets. The planarized surface allows for increased signal integrity and reduced insertion loss and the irregular surface allows for increased adhesion and enhancing reliability of the circuit apparatus.Type: GrantFiled: April 29, 2019Date of Patent: March 17, 2020Assignee: International Business Machines CorporationInventors: Brian L. Carlson, John R. Dangler, Roger S. Krabbenhoft, Kevin A. Splittstoesser
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Patent number: 10390439Abstract: A circuit apparatus includes at least one circuit feature formed from patterning a conductive sheet. The conductive sheet includes an irregular surface and a planarized surface. Conductive sheet roughness is minimized in first regions of the circuit apparatus and is maintained in second regions of the circuit apparatus. Selectively planarizing portions of the conductive sheet allows for the utilization of lower cost rougher conductive sheets. The planarized surface allows for increased signal integrity and reduced insertion loss and the irregular surface allows for increased adhesion and enhancing reliability of the circuit apparatus.Type: GrantFiled: December 12, 2017Date of Patent: August 20, 2019Assignee: International Business Machines CorporationInventors: Brian L. Carlson, John R. Dangler, Roger S. Krabbenhoft, Kevin A. Splittstoesser
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Publication number: 20190254172Abstract: A circuit apparatus includes a first circuit feature upon a first insulator and a second circuit feature upon the first insulator. The first circuit feature includes a planarized surface and the second circuit feature includes an irregular surface. The first circuit feature and the second circuit feature may be formed from patterning a conductive sheet that is upon the first insulator. The conductive sheet includes an irregular surface and a planarized surface. Conductive sheet roughness is minimized in first regions thereof and is maintained in second regions thereof. Selectively planarizing portions of the conductive sheet allows for the utilization of lower cost rougher conductive sheets. The planarized surface allows for increased signal integrity and reduced insertion loss and the irregular surface allows for increased adhesion and enhancing reliability of the circuit apparatus.Type: ApplicationFiled: April 29, 2019Publication date: August 15, 2019Inventors: Brian L. Carlson, John R. Dangler, Roger S. Krabbenhoft, Kevin A. Splittstoesser
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Patent number: 10378925Abstract: Electronic circuits, electronic packages, and methods of fabrication are provided. The electronic circuit includes a multilayer circuit board, and a tamper-respondent sensor embedded within the circuit board. The tamper-respondent sensor defines, at least in part, a secure volume associated with the multilayer circuit board. In certain implementations, the tamper-respondent sensor includes multiple tamper-respondent layers embedded within the circuit board including, for instance, one or more tamper-respondent frames and one or more tamper-respondent mat layers, with the tamper-respondent frame(s) being disposed, at least in part, above the tamper-respondent mat layer(s), which together define the secure volume where extending into the multilayer circuit board.Type: GrantFiled: October 17, 2018Date of Patent: August 13, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William L. Brodsky, Silvio Dragone, Roger S. Krabbenhoft, David C. Long, Stefano S. Oggioni, Michael T. Peets, William Santiago-Fernandez
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Patent number: 10378924Abstract: Methods of fabricating electronic circuits and electronic packages are provided. The electronic circuit includes a multilayer circuit board, and a tamper-respondent sensor embedded within the circuit board. The tamper-respondent sensor defines, at least in part, a secure volume associated with the multilayer circuit board. In certain implementations, the tamper-respondent sensor includes multiple tamper-respondent layers embedded within the circuit board including, for instance, one or more tamper-respondent frames and one or more tamper-respondent mat layers, with the tamper-respondent frame(s) being disposed, at least in part, above the tamper-respondent mat layer(s), which together define the secure volume where extending into the multilayer circuit board.Type: GrantFiled: September 20, 2018Date of Patent: August 13, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William L. Brodsky, Silvio Dragone, Roger S. Krabbenhoft, David C. Long, Stefano S. Oggioni, Michael T. Peets, William Santiago-Fernandez
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Publication number: 20190049269Abstract: Electronic circuits, electronic packages, and methods of fabrication are provided. The electronic circuit includes a multilayer circuit board, and a tamper-respondent sensor embedded within the circuit board. The tamper-respondent sensor defines, at least in part, a secure volume associated with the multilayer circuit board. In certain implementations, the tamper-respondent sensor includes multiple tamper-respondent layers embedded within the circuit board including, for instance, one or more tamper-respondent frames and one or more tamper-respondent mat layers, with the tamper-respondent frame(s) being disposed, at least in part, above the tamper-respondent mat layer(s), which together define the secure volume where extending into the multilayer circuit board.Type: ApplicationFiled: October 17, 2018Publication date: February 14, 2019Inventors: William L. BRODSKY, Silvio DRAGONE, Roger S. KRABBENHOFT, David C. LONG, Stefano S. OGGIONI, Michael T. PEETS, William SANTIAGO-FERNANDEZ
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Publication number: 20190017844Abstract: Methods of fabricating electronic circuits and electronic packages are provided. The electronic circuit includes a multilayer circuit board, and a tamper-respondent sensor embedded within the circuit board. The tamper-respondent sensor defines, at least in part, a secure volume associated with the multilayer circuit board. In certain implementations, the tamper-respondent sensor includes multiple tamper-respondent layers embedded within the circuit board including, for instance, one or more tamper-respondent frames and one or more tamper-respondent mat layers, with the tamper-respondent frame(s) being disposed, at least in part, above the tamper-respondent mat layer(s), which together define the secure volume where extending into the multilayer circuit board.Type: ApplicationFiled: September 20, 2018Publication date: January 17, 2019Inventors: William L. BRODSKY, Silvio DRAGONE, Roger S. KRABBENHOFT, David C. LONG, Stefano S. OGGIONI, Michael T. PEETS, William SANTIAGO-FERNANDEZ
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Patent number: 10175064Abstract: Electronic circuits, electronic packages, and methods of fabrication are provided. The electronic circuit includes a multilayer circuit board, and a tamper-respondent sensor embedded within the circuit board. The tamper-respondent sensor defines, at least in part, a secure volume associated with the multilayer circuit board. In certain implementations, the tamper-respondent sensor includes multiple tamper-respondent layers embedded within the circuit board including, for instance, one or more tamper-respondent frames and one or more tamper-respondent mat layers, with the tamper-respondent frame(s) being disposed, at least in part, above the tamper-respondent mat layer(s), which together define the secure volume where extending into the multilayer circuit board.Type: GrantFiled: September 25, 2015Date of Patent: January 8, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William L. Brodsky, Silvio Dragone, Roger S. Krabbenhoft, David C. Long, Stefano S. Oggioni, Michael T. Peets, William Santiago-Fernandez
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Patent number: 10168185Abstract: Methods of fabricating electronic circuits and electronic packages are provided. The electronic circuit includes a multilayer circuit board, and a tamper-respondent sensor embedded within the circuit board. The tamper-respondent sensor defines, at least in part, a secure volume associated with the multilayer circuit board. In certain implementations, the tamper-respondent sensor includes multiple tamper-respondent layers embedded within the circuit board including, for instance, one or more tamper-respondent frames and one or more tamper-respondent mat layers, with the tamper-respondent frame(s) being disposed, at least in part, above the tamper-respondent mat layer(s), which together define the secure volume where extending into the multilayer circuit board.Type: GrantFiled: November 16, 2015Date of Patent: January 1, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William L. Brodsky, Silvio Dragone, Roger S. Krabbenhoft, David C. Long, Stefano S. Oggioni, Michael T. Peets, William Santiago-Fernandez
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Publication number: 20180228023Abstract: A process of forming an angled fiberglass cloth weave includes weaving a first set of fibers oriented at a first non-orthogonal angle with respect to a printed circuit board to be formed from the angled fiberglass cloth weave with a second set of fibers oriented at a second non-orthogonal angle with respect to the printed circuit board to be formed form the angled fiberglass cloth weave.Type: ApplicationFiled: February 9, 2017Publication date: August 9, 2018Inventors: MICHAEL A. CHRISTO, JOSE A. HEJASE, ROGER S. KRABBENHOFT, DIANA D. ZUROVETZ
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Publication number: 20180113974Abstract: Mechanisms are provided for implementing a skew rate artificial neural network (ANN). The mechanisms generate a training dataset for training the skew rate ANN. The training dataset comprises a plurality of sets of data and each set of data corresponds to a particular set of printed circuit board (PCB) and communication channel characteristics. The mechanisms train the skew rate ANN based on the training dataset to generate a trained skew rate ANN. The mechanisms then receive an input dataset representing a set of PCB and communication channel characteristics for a PCB design. The trained skew rate ANN generates a predicted skew factor for the PCB design based on the input dataset. The predicted skew factor is then output to a PCB design tool to modify the PCB design based on the predicted skew factor.Type: ApplicationFiled: October 21, 2016Publication date: April 26, 2018Inventors: Dylan J. Boday, Zhaoqing Chen, Jose A. Hejase, Roger S. Krabbenhoft, Pavel Roy Paladhi, Junyan Tang
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Patent number: 9949357Abstract: The embodiments relate to a method for integrating a venting system in a circuit board. Three or more interconnected accesses (VIAs) are formed in a printed circuit board (PCB). The VIAs are interconnected by routing a bi-planar channel spanning through the VIAs. The channel includes at least two sections, including a first channel section at a first plane extending from the first VIA to the second VIA and a second channel section at a second plane extending from the second VIA to the third VIA. The first and second sections are at different planar levels.Type: GrantFiled: October 20, 2015Date of Patent: April 17, 2018Assignee: International Business Machines CorporationInventors: Michael J. Fisher, Roger S. Krabbenhoft
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Publication number: 20180103548Abstract: A circuit apparatus includes at least one circuit feature formed from patterning a conductive sheet. The conductive sheet includes an irregular surface and a planarized surface. Conductive sheet roughness is minimized in first regions of the circuit apparatus and is maintained in second regions of the circuit apparatus. Selectively planarizing portions of the conductive sheet allows for the utilization of lower cost rougher conductive sheets. The planarized surface allows for increased signal integrity and reduced insertion loss and the irregular surface allows for increased adhesion and enhancing reliability of the circuit apparatus.Type: ApplicationFiled: December 12, 2017Publication date: April 12, 2018Inventors: Brian L. Carlson, John R. Dangler, Roger S. Krabbenhoft, Kevin A. Splittstoesser
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Patent number: 9942990Abstract: A circuit apparatuses include at least one circuit feature formed from patterning a conductive sheet. The conductive sheet includes an irregular surface and a planarized surface. Conductive sheet roughness is minimized in first regions of the circuit apparatus and is maintained in second regions of the circuit apparatus. Selectively planarizing portions of the conductive sheet allows for the utilization of lower cost rougher conductive sheets. The planarized surface allows for increased signal integrity and reduced insertion loss and the irregular surface allows for increased adhesion and enhancing reliability of the circuit apparatus.Type: GrantFiled: August 24, 2016Date of Patent: April 10, 2018Assignee: International Business Machines CorporationInventors: Brian L. Carlson, John R. Dangler, Roger S. Krabbenhoft, Kevin A. Splittstoesser
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Patent number: 9930768Abstract: The embodiments relate to a method for integrating a venting system in a circuit board. Three or more interconnected accesses (VIAs) are formed in a printed circuit board (PCB). The VIAs are interconnected by routing a bi-planar channel spanning through the VIAs. The channel includes at least two sections, including a first channel section at a first plane extending from the first VIA to the second VIA and a second channel section at a second plane extending from the second VIA to the third VIA. The first and second sections are at different planar levels.Type: GrantFiled: November 14, 2016Date of Patent: March 27, 2018Assignee: International Business Machine CorporationInventors: Michael J. Fisher, Roger S. Krabbenhoft
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Patent number: 9648723Abstract: A circuit apparatuses include at least one circuit feature formed from patterning a conductive sheet. The conductive sheet includes an irregular surface and a planarized surface. Conductive sheet roughness is minimized in first regions of the circuit apparatus and is maintained in second regions of the circuit apparatus. Selectively planarizing portions of the conductive sheet allows for the utilization of lower cost rougher conductive sheets. The planarized surface allows for increased signal integrity and reduced insertion loss and the irregular surface allows for increased adhesion and enhancing reliability of the circuit apparatus.Type: GrantFiled: September 16, 2015Date of Patent: May 9, 2017Assignee: International Business Machines CorporationInventors: Brian L. Carlson, John R. Dangler, Roger S. Krabbenhoft, Kevin A. Splittstoesser
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Publication number: 20170089729Abstract: Electronic circuits, electronic packages, and methods of fabrication are provided. The electronic circuit includes a multilayer circuit board, and a tamper-respondent sensor embedded within the circuit board. The tamper-respondent sensor defines, at least in part, a secure volume associated with the multilayer circuit board. In certain implementations, the tamper-respondent sensor includes multiple tamper-respondent layers embedded within the circuit board including, for instance, one or more tamper-respondent frames and one or more tamper-respondent mat layers, with the tamper-respondent frame(s) being disposed, at least in part, above the tamper-respondent mat layer(s), which together define the secure volume where extending into the multilayer circuit board.Type: ApplicationFiled: September 25, 2015Publication date: March 30, 2017Inventors: William L. BRODSKY, Silvio DRAGONE, Roger S. KRABBENHOFT, David C. LONG, Stefano S. OGGIONI, Michael T. PEETS, William SANTIAGO-FERNANDEZ