Abstract: Methods of fabricating electronic circuits and electronic packages are provided. The electronic circuit includes a multilayer circuit board, and a tamper-respondent sensor embedded within the circuit board. The tamper-respondent sensor defines, at least in part, a secure volume associated with the multilayer circuit board. In certain implementations, the tamper-respondent sensor includes multiple tamper-respondent layers embedded within the circuit board including, for instance, one or more tamper-respondent frames and one or more tamper-respondent mat layers, with the tamper-respondent frame(s) being disposed, at least in part, above the tamper-respondent mat layer(s), which together define the secure volume where extending into the multilayer circuit board.

Abstract: A circuit apparatuses include at least one circuit feature formed from patterning a conductive sheet. The conductive sheet includes an irregular surface and a planarized surface. Conductive sheet roughness is minimized in first regions of the circuit apparatus and is maintained in second regions of the circuit apparatus. Selectively planarizing portions of the conductive sheet allows for the utilization of lower cost rougher conductive sheets. The planarized surface allows for increased signal integrity and reduced insertion loss and the irregular surface allows for increased adhesion and enhancing reliability of the circuit apparatus.

Abstract: A circuit apparatuses include at least one circuit feature formed from patterning a conductive sheet. The conductive sheet includes an irregular surface and a planarized surface. Conductive sheet roughness is minimized in first regions of the circuit apparatus and is maintained in second regions of the circuit apparatus. Selectively planarizing portions of the conductive sheet allows for the utilization of lower cost rougher conductive sheets. The planarized surface allows for increased signal integrity and reduced insertion loss and the irregular surface allows for increased adhesion and enhancing reliability of the circuit apparatus.

Abstract: The embodiments relate to a method for integrating a venting system in a circuit board. Three or more interconnected accesses (VIAs) are formed in a printed circuit board (PCB). The VIAs are interconnected by routing a bi-planar channel spanning through the VIAs. The channel includes at least two sections, including a first channel section at a first plane extending from the first VIA to the second VIA and a second channel section at a second plane extending from the second VIA to the third VIA. The first and second sections are at different planar levels.

Abstract: The embodiments relate to integrating a venting system in a circuit board. Three or more interconnected accesses (VIAs) are formed in a printed circuit board (PCB). The VIAs are interconnected by routing a bi-planar channel spanning through the VIAs. The channel includes at least two sections, including a first channel section at a first plane extending from the first VIA to the second VIA and a second channel section at a second plane extending from the second VIA to the third VIA. The first and second sections are at different planar levels.

Abstract: The embodiments relate to integrating a venting system in a circuit board. Three or more interconnected accesses (VIAs) are formed in a printed circuit board (PCB). The VIAs are interconnected by routing a bi-planar channel spanning through the VIAs. The channel includes at least two sections, including a first channel section at a first plane extending from the first VIA to the second VIA and a second channel section at a second plane extending from the second VIA to the third VIA. The first and second sections are at different planar levels.

Abstract: The embodiments relate to a method for integrating a venting system in a circuit board. Three or more interconnected accesses (VIAs) are formed in a printed circuit board (PCB). The VIAs are interconnected by routing a bi-planar channel spanning through the VIAs. The channel includes at least two sections, including a first channel section at a first plane extending from the first VIA to the second VIA and a second channel section at a second plane extending from the second VIA to the third VIA. The first and second sections are at different planar levels.

Abstract: A method and apparatus are provided for implementing electrical connection of two large circuit cards through multiple discrete land grid array (LGA) sites. Each of the circuit cards includes a plurality of LGA sites. A first circuit card includes a plurality of LGA interposers locally aligned at the respective LGA sites of the first circuit card. A board-to-board connection hardware assembly connecting a second circuit card to the first circuit card includes a elongated carrier defining a cavity receiving a plurality of load springs coupled to an associated bearing block for loading and maintaining flatness of the LGA sites.

Abstract: A method and apparatus are provided for implementing electrical connection of two large circuit cards through multiple discrete land grid array (LGA) sites. Each of the circuit cards includes a plurality of LGA sites. A first circuit card includes a plurality of LGA interposers locally aligned at the respective LGA sites of the first circuit card. A board-to-board connection hardware assembly connecting a second circuit card to the first circuit card includes a elongated carrier defining a cavity receiving a plurality of load springs coupled to an associated bearing block for loading and maintaining flatness of the LGA sites.

Abstract: A total cost estimate is calculated based on a set of printed circuit board (PCB) design parameters. The set of PCB design parameters are received, and PCB attributes are extracted from them. Based on the PCB attributes the PCB is classified and a cost equation is calculated. The cost equation is calculated based on a regression analysis of one or more of the PCB attributes. Once the cost equation is calculated, the total cost is computed based on the cost equation.

Abstract: A method, a computer program product, and an apparatus is provided for scheduling meetings which includes (1) evaluating a set of proposed meetings, (2) creating a number of calendars, each calendar containing schedule date for the proposed meetings, (3) ranking each calendar according to a calendar evaluation criteria and providing the ranking data with the calendar, and (4) displaying several of the calendars and their respective ranking data.

Abstract: A system and method for performing a test for characterizing high frequency operation of PCB boards. More particularly, a system and methodology is provided to implement a time-domain short pulse propagation (SPP) technique on the production line, on large, multi-layer, product-level PCB boards, for large volume testing, by people who are not familiar with advanced, delicate, measurement techniques, who need robust test facilities, and cannot afford the time or expense of other lab-type approaches.

Abstract: A system and method for performing a test for characterizing high frequency operation of PCB boards. More particularly, a system and methodology is provided to implement a time-domain short pulse propagation (SPP) technique on the production line, on large, multi-layer, product-level PCB boards, for large volume testing, by people who are not familiar with advanced, delicate, measurement techniques, who need robust test facilities, and cannot afford the time or expense of other lab-type approaches.

Abstract: A printed circuit connector terminal pad coating technique is disclosed which functions as a single universal pad surface which supports multiple electrical connection practices including wirebonding, soldering, and wear resistant, pad on pad mechanical connection. The tri-plate surface treatment includes an initial diffusion resistant coating of nickel; an intermediate layer of hard, wear resistant noble or semi-noble metal that provides pad on pad connector reliability and affords a metallurgically stable solder joints and wirebond interfaces; and a final coating of soft gold. The intermediate layer may be pure palladium having a nominal thickness of 35 microinches or a layer of gold, hardened by cobalt, nickel, iron or a combination of these dopants to effect a hardness of 200 to 250 (Knoop scale). The use of a common surface treatment for the multiple attachment processes is implemented with a single masking step, rather than a sequence of selective masking, plating and stripping operations.