Patents by Inventor Rohit Kothari

Rohit Kothari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12092953
    Abstract: Various embodiments disclosed relate to methods of manufacturing a textured surface comprising disposing a nanoparticulate ink on a substrate.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: September 17, 2024
    Assignee: University of Massachusetts
    Inventors: James J. Watkins, Rohit Kothari
  • Patent number: 12057114
    Abstract: A media content steering solution is provided to identify a user query to steer playback of media content that is currently playing or has been played. The user steering query can include a voice request for playing media content that is relatively different from the media content being currently played or having been played. The media content steering solution analyzes the utterance of the user query and uses it to identify such different content that satisfies the user intent contained in the user query.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: August 6, 2024
    Assignee: Spotify AB
    Inventors: Bryan Roy, Philip Edmonds, Matthew Joseph Kane, Jennifer Thom-Santelli, Neha Kothari, Sarah Mennicken, Karl Humphreys, Ruth Brillman, Sravana Reddy, Henriette Cramer, Robert L. Williams, Rohit Kumar
  • Publication number: 20240186267
    Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.
    Type: Application
    Filed: February 15, 2024
    Publication date: June 6, 2024
    Inventors: Rohit Kothari, Adam L. Olson, John D. Hopkins, Jeslin J. Wu
  • Patent number: 11916024
    Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: February 27, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Rohit Kothari, Adam L Olson, John D. Hopkins, Jeslin J. Wu
  • Publication number: 20230354595
    Abstract: Methods of improving adhesion between a photoresist and conductive or insulating structures. The method comprises forming a slot through at least a portion of alternating conductive structures and insulating structures on a substrate. Portions of the conductive structures or of the insulating structures are removed to form recesses in the conductive structures or in the insulating structures. A photoresist is formed over the alternating conductive structures and insulating structures and within the slot. Methods of improving adhesion between a photoresist and a spin-on dielectric material are also disclosed, as well as methods of forming a staircase structure.
    Type: Application
    Filed: June 12, 2023
    Publication date: November 2, 2023
    Inventors: Rohit Kothari, Jason C. McFarland, Jason Reece, David A. Kewley, Adam L. Olson
  • Publication number: 20230197627
    Abstract: An electronic device comprising a multideck structure including a base stack of materials and one or more stacks of materials on the base stack of materials, at least one high aspect ratio feature in an array region in the base stack of materials and in the one or more stacks of materials, and overlay marks including an optical contrast material in or on only an upper portion of the base stack of materials in an overlay mark region of the electronic device is disclosed. The overlay mark region is laterally adjacent to the array region and the overlay marks are adjacent to at least one additional high aspect ratio feature in the base stack of materials. Additional electronic devices and memory devices are disclosed.
    Type: Application
    Filed: February 13, 2023
    Publication date: June 22, 2023
    Inventors: Rohit Kothari, Harsh Narendrakumar Jain, John D. Hopkins, Xiaosong Zhang
  • Patent number: 11678481
    Abstract: Methods of improving adhesion between a photoresist and conductive or insulating structures. The method comprises forming a slot through at least a portion of alternating conductive structures and insulating structures on a substrate. Portions of the conductive structures or of the insulating structures are removed to form recesses in the conductive structures or in the insulating structures. A photoresist is formed over the alternating conductive structures and insulating structures and within the slot. Methods of improving adhesion between a photoresist and a spin-on dielectric material are also disclosed, as well as methods of forming a staircase structure.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: June 13, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Rohit Kothari, Jason C. McFarland, Jason Reece, David A. Kewley, Adam L. Olson
  • Patent number: 11658132
    Abstract: Some embodiments include an integrated assembly having a semiconductor die with memory array regions and one or more regions peripheral to the memory array regions. A stack of alternating insulative and conductive levels extends across the memory array regions and passes into at least one of the peripheral regions. The stack generates bending stresses on the die. At least one stress-moderating region extends through the stack and is configured to alleviate the bending stresses.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: May 23, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Rohit Kothari, Lifang Xu, Jian Li
  • Patent number: 11581264
    Abstract: An electronic device comprising at least one high aspect ratio feature in a base stack of materials, overlay marks in or on only an upper portion of the base stack of materials, and an additional stack of materials adjacent the base stack of materials, the additional stack of materials comprising the at least one high aspect ratio feature. Additional electronic devices and memory devices are disclosed, as are methods of forming high aspect ratio features in an electronic device.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: February 14, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Rohit Kothari, Harsh Narendrakumar Jain, John D. Hopkins, Xiaosong Zhang
  • Publication number: 20220115335
    Abstract: Some embodiments include an integrated assembly having a semiconductor die with memory array regions and one or more regions peripheral to the memory array regions. A stack of alternating insulative and conductive levels extends across the memory array regions and passes into at least one of the peripheral regions. The stack generates bending stresses on the die. At least one stress-moderating region extends through the stack and is configured to alleviate the bending stresses.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Rohit Kothari, Lifang Xu, Jian Li
  • Patent number: 11239181
    Abstract: Some embodiments include an integrated assembly having a semiconductor die with memory array regions and one or more regions peripheral to the memory array regions. A stack of alternating insulative and conductive levels extends across the memory array regions and passes into at least one of the peripheral regions. The stack generates bending stresses on the die. At least one stress-moderating region extends through the stack and is configured to alleviate the bending stresses.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: February 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Rohit Kothari, Lifang Xu, Jian Li
  • Publication number: 20210407930
    Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.
    Type: Application
    Filed: September 14, 2021
    Publication date: December 30, 2021
    Inventors: Rohit Kothari, Adam L. Olson, John D. Hopkins, Jeslin J. Wu
  • Patent number: 11127691
    Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: September 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Rohit Kothari, Adam L. Olson, John D. Hopkins, Jeslin J. Wu
  • Publication number: 20210167079
    Abstract: Methods of improving adhesion between a photoresist and conductive or insulating structures. The method comprises forming a slot through at least a portion of alternating conductive structures and insulating structures on a substrate. Portions of the conductive structures or of the insulating structures are removed to form recesses in the conductive structures or in the insulating structures. A photoresist is formed over the alternating conductive structures and insulating structures and within the slot. Methods of improving adhesion between a photoresist and a spin-on dielectric material are also disclosed, as well as methods of forming a staircase structure.
    Type: Application
    Filed: February 11, 2021
    Publication date: June 3, 2021
    Inventors: Rohit Kothari, Jason C. McFarland, Jason Reece, David A. Kewley, Adam L. Olson
  • Publication number: 20210125939
    Abstract: Some embodiments include an integrated assembly having a semiconductor die with memory array regions and one or more regions peripheral to the memory array regions. A stack of alternating insulative and conductive levels extends across the memory array regions and passes into at least one of the peripheral regions. The stack generates bending stresses on the die. At least one stress-moderating region extends through the stack and is configured to alleviate the bending stresses.
    Type: Application
    Filed: October 24, 2019
    Publication date: April 29, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Rohit Kothari, Lifang Xu, Jian Li
  • Publication number: 20210057349
    Abstract: An electronic device comprising at least one high aspect ratio feature in a base stack of materials, overlay marks in or on only an upper portion of the base stack of materials, and an additional stack of materials adjacent the base stack of materials, the additional stack of materials comprising the at least one high aspect ratio feature. Additional electronic devices and memory devices are disclosed, as are methods of forming high aspect ratio features in an electronic device.
    Type: Application
    Filed: August 21, 2019
    Publication date: February 25, 2021
    Inventors: Rohit Kothari, Harsh Narendrakumar Jain, John D. Hopkins, Xiaosong Zhang
  • Patent number: 10930659
    Abstract: Methods of improving adhesion between a photoresist and conductive or insulating structures. The method comprises forming a slot through at least a portion of alternating conductive structures and insulating structures on a substrate. Portions of the conductive structures or of the insulating structures are removed to form recesses in the conductive structures or in the insulating structures. A photoresist is formed over the alternating conductive structures and insulating structures and within the slot. Methods of improving adhesion between a photoresist and a spin-on dielectric material are also disclosed, as well as methods of forming a staircase structure.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: February 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Rohit Kothari, Jason C. McFarland, Jason Reece, David A. Kewley, Adam L. Olson
  • Publication number: 20200211981
    Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: Rohit Kothari, Adam L. Olson, John D. Hopkins, Jeslin J. Wu
  • Patent number: 10600796
    Abstract: Methods of improving adhesion between a photoresist and conductive or insulating structures. The method comprises forming a slot through at least a portion of alternating conductive structures and insulating structures on a substrate. Portions of the conductive structures or of the insulating structures are removed to form recesses in the conductive structures or in the insulating structures. A photoresist is formed over the alternating conductive structures and insulating structures and within the slot. Methods of improving adhesion between a photoresist and a spin-on dielectric material are also disclosed, as well as methods of forming a staircase structure.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: March 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Rohit Kothari, Jason C. McFarland, Jason Reece, David A. Kewley, Adam L. Olson
  • Publication number: 20190355735
    Abstract: Methods of improving adhesion between a photoresist and conductive or insulating structures. The method comprises forming a slot through at least a portion of alternating conductive structures and insulating structures on a substrate. Portions of the conductive structures or of the insulating structures are removed to form recesses in the conductive structures or in the insulating structures. A photoresist is formed over the alternating conductive structures and insulating structures and within the slot. Methods of improving adhesion between a photoresist and a spin-on dielectric material are also disclosed, as well as methods of forming a staircase structure.
    Type: Application
    Filed: August 5, 2019
    Publication date: November 21, 2019
    Inventors: Rohit Kothari, Jason C. McFarland, Jason Reece, David A. Kewley, Adam L. Olson