Patents by Inventor Rohit Kothari
Rohit Kothari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12092953Abstract: Various embodiments disclosed relate to methods of manufacturing a textured surface comprising disposing a nanoparticulate ink on a substrate.Type: GrantFiled: June 26, 2017Date of Patent: September 17, 2024Assignee: University of MassachusettsInventors: James J. Watkins, Rohit Kothari
-
Patent number: 12057114Abstract: A media content steering solution is provided to identify a user query to steer playback of media content that is currently playing or has been played. The user steering query can include a voice request for playing media content that is relatively different from the media content being currently played or having been played. The media content steering solution analyzes the utterance of the user query and uses it to identify such different content that satisfies the user intent contained in the user query.Type: GrantFiled: September 12, 2019Date of Patent: August 6, 2024Assignee: Spotify ABInventors: Bryan Roy, Philip Edmonds, Matthew Joseph Kane, Jennifer Thom-Santelli, Neha Kothari, Sarah Mennicken, Karl Humphreys, Ruth Brillman, Sravana Reddy, Henriette Cramer, Robert L. Williams, Rohit Kumar
-
Publication number: 20240186267Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.Type: ApplicationFiled: February 15, 2024Publication date: June 6, 2024Inventors: Rohit Kothari, Adam L. Olson, John D. Hopkins, Jeslin J. Wu
-
Patent number: 11916024Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.Type: GrantFiled: September 14, 2021Date of Patent: February 27, 2024Assignee: Micron Technology, Inc.Inventors: Rohit Kothari, Adam L Olson, John D. Hopkins, Jeslin J. Wu
-
Publication number: 20230354595Abstract: Methods of improving adhesion between a photoresist and conductive or insulating structures. The method comprises forming a slot through at least a portion of alternating conductive structures and insulating structures on a substrate. Portions of the conductive structures or of the insulating structures are removed to form recesses in the conductive structures or in the insulating structures. A photoresist is formed over the alternating conductive structures and insulating structures and within the slot. Methods of improving adhesion between a photoresist and a spin-on dielectric material are also disclosed, as well as methods of forming a staircase structure.Type: ApplicationFiled: June 12, 2023Publication date: November 2, 2023Inventors: Rohit Kothari, Jason C. McFarland, Jason Reece, David A. Kewley, Adam L. Olson
-
Publication number: 20230197627Abstract: An electronic device comprising a multideck structure including a base stack of materials and one or more stacks of materials on the base stack of materials, at least one high aspect ratio feature in an array region in the base stack of materials and in the one or more stacks of materials, and overlay marks including an optical contrast material in or on only an upper portion of the base stack of materials in an overlay mark region of the electronic device is disclosed. The overlay mark region is laterally adjacent to the array region and the overlay marks are adjacent to at least one additional high aspect ratio feature in the base stack of materials. Additional electronic devices and memory devices are disclosed.Type: ApplicationFiled: February 13, 2023Publication date: June 22, 2023Inventors: Rohit Kothari, Harsh Narendrakumar Jain, John D. Hopkins, Xiaosong Zhang
-
Patent number: 11678481Abstract: Methods of improving adhesion between a photoresist and conductive or insulating structures. The method comprises forming a slot through at least a portion of alternating conductive structures and insulating structures on a substrate. Portions of the conductive structures or of the insulating structures are removed to form recesses in the conductive structures or in the insulating structures. A photoresist is formed over the alternating conductive structures and insulating structures and within the slot. Methods of improving adhesion between a photoresist and a spin-on dielectric material are also disclosed, as well as methods of forming a staircase structure.Type: GrantFiled: February 11, 2021Date of Patent: June 13, 2023Assignee: Micron Technology, Inc.Inventors: Rohit Kothari, Jason C. McFarland, Jason Reece, David A. Kewley, Adam L. Olson
-
Patent number: 11658132Abstract: Some embodiments include an integrated assembly having a semiconductor die with memory array regions and one or more regions peripheral to the memory array regions. A stack of alternating insulative and conductive levels extends across the memory array regions and passes into at least one of the peripheral regions. The stack generates bending stresses on the die. At least one stress-moderating region extends through the stack and is configured to alleviate the bending stresses.Type: GrantFiled: December 22, 2021Date of Patent: May 23, 2023Assignee: Micron Technology, Inc.Inventors: Rohit Kothari, Lifang Xu, Jian Li
-
Patent number: 11581264Abstract: An electronic device comprising at least one high aspect ratio feature in a base stack of materials, overlay marks in or on only an upper portion of the base stack of materials, and an additional stack of materials adjacent the base stack of materials, the additional stack of materials comprising the at least one high aspect ratio feature. Additional electronic devices and memory devices are disclosed, as are methods of forming high aspect ratio features in an electronic device.Type: GrantFiled: August 21, 2019Date of Patent: February 14, 2023Assignee: Micron Technology, Inc.Inventors: Rohit Kothari, Harsh Narendrakumar Jain, John D. Hopkins, Xiaosong Zhang
-
Publication number: 20220115335Abstract: Some embodiments include an integrated assembly having a semiconductor die with memory array regions and one or more regions peripheral to the memory array regions. A stack of alternating insulative and conductive levels extends across the memory array regions and passes into at least one of the peripheral regions. The stack generates bending stresses on the die. At least one stress-moderating region extends through the stack and is configured to alleviate the bending stresses.Type: ApplicationFiled: December 22, 2021Publication date: April 14, 2022Applicant: Micron Technology, Inc.Inventors: Rohit Kothari, Lifang Xu, Jian Li
-
Patent number: 11239181Abstract: Some embodiments include an integrated assembly having a semiconductor die with memory array regions and one or more regions peripheral to the memory array regions. A stack of alternating insulative and conductive levels extends across the memory array regions and passes into at least one of the peripheral regions. The stack generates bending stresses on the die. At least one stress-moderating region extends through the stack and is configured to alleviate the bending stresses.Type: GrantFiled: October 24, 2019Date of Patent: February 1, 2022Assignee: Micron Technology, Inc.Inventors: Rohit Kothari, Lifang Xu, Jian Li
-
Publication number: 20210407930Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.Type: ApplicationFiled: September 14, 2021Publication date: December 30, 2021Inventors: Rohit Kothari, Adam L. Olson, John D. Hopkins, Jeslin J. Wu
-
Patent number: 11127691Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.Type: GrantFiled: December 28, 2018Date of Patent: September 21, 2021Assignee: Micron Technology, Inc.Inventors: Rohit Kothari, Adam L. Olson, John D. Hopkins, Jeslin J. Wu
-
Publication number: 20210167079Abstract: Methods of improving adhesion between a photoresist and conductive or insulating structures. The method comprises forming a slot through at least a portion of alternating conductive structures and insulating structures on a substrate. Portions of the conductive structures or of the insulating structures are removed to form recesses in the conductive structures or in the insulating structures. A photoresist is formed over the alternating conductive structures and insulating structures and within the slot. Methods of improving adhesion between a photoresist and a spin-on dielectric material are also disclosed, as well as methods of forming a staircase structure.Type: ApplicationFiled: February 11, 2021Publication date: June 3, 2021Inventors: Rohit Kothari, Jason C. McFarland, Jason Reece, David A. Kewley, Adam L. Olson
-
Publication number: 20210125939Abstract: Some embodiments include an integrated assembly having a semiconductor die with memory array regions and one or more regions peripheral to the memory array regions. A stack of alternating insulative and conductive levels extends across the memory array regions and passes into at least one of the peripheral regions. The stack generates bending stresses on the die. At least one stress-moderating region extends through the stack and is configured to alleviate the bending stresses.Type: ApplicationFiled: October 24, 2019Publication date: April 29, 2021Applicant: Micron Technology, Inc.Inventors: Rohit Kothari, Lifang Xu, Jian Li
-
Publication number: 20210057349Abstract: An electronic device comprising at least one high aspect ratio feature in a base stack of materials, overlay marks in or on only an upper portion of the base stack of materials, and an additional stack of materials adjacent the base stack of materials, the additional stack of materials comprising the at least one high aspect ratio feature. Additional electronic devices and memory devices are disclosed, as are methods of forming high aspect ratio features in an electronic device.Type: ApplicationFiled: August 21, 2019Publication date: February 25, 2021Inventors: Rohit Kothari, Harsh Narendrakumar Jain, John D. Hopkins, Xiaosong Zhang
-
Patent number: 10930659Abstract: Methods of improving adhesion between a photoresist and conductive or insulating structures. The method comprises forming a slot through at least a portion of alternating conductive structures and insulating structures on a substrate. Portions of the conductive structures or of the insulating structures are removed to form recesses in the conductive structures or in the insulating structures. A photoresist is formed over the alternating conductive structures and insulating structures and within the slot. Methods of improving adhesion between a photoresist and a spin-on dielectric material are also disclosed, as well as methods of forming a staircase structure.Type: GrantFiled: August 5, 2019Date of Patent: February 23, 2021Assignee: Micron Technology, Inc.Inventors: Rohit Kothari, Jason C. McFarland, Jason Reece, David A. Kewley, Adam L. Olson
-
Publication number: 20200211981Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.Type: ApplicationFiled: December 28, 2018Publication date: July 2, 2020Inventors: Rohit Kothari, Adam L. Olson, John D. Hopkins, Jeslin J. Wu
-
Patent number: 10600796Abstract: Methods of improving adhesion between a photoresist and conductive or insulating structures. The method comprises forming a slot through at least a portion of alternating conductive structures and insulating structures on a substrate. Portions of the conductive structures or of the insulating structures are removed to form recesses in the conductive structures or in the insulating structures. A photoresist is formed over the alternating conductive structures and insulating structures and within the slot. Methods of improving adhesion between a photoresist and a spin-on dielectric material are also disclosed, as well as methods of forming a staircase structure.Type: GrantFiled: June 15, 2017Date of Patent: March 24, 2020Assignee: Micron Technology, Inc.Inventors: Rohit Kothari, Jason C. McFarland, Jason Reece, David A. Kewley, Adam L. Olson
-
Publication number: 20190355735Abstract: Methods of improving adhesion between a photoresist and conductive or insulating structures. The method comprises forming a slot through at least a portion of alternating conductive structures and insulating structures on a substrate. Portions of the conductive structures or of the insulating structures are removed to form recesses in the conductive structures or in the insulating structures. A photoresist is formed over the alternating conductive structures and insulating structures and within the slot. Methods of improving adhesion between a photoresist and a spin-on dielectric material are also disclosed, as well as methods of forming a staircase structure.Type: ApplicationFiled: August 5, 2019Publication date: November 21, 2019Inventors: Rohit Kothari, Jason C. McFarland, Jason Reece, David A. Kewley, Adam L. Olson