Patents by Inventor Rohit Pal

Rohit Pal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11224915
    Abstract: A method for forming a secondary component from an original component having an original shape includes separating the original component into a parent component and a replaced portion, and forming a replacement coupon using an additive manufacturing system. The replacement coupon is shaped to substantially match the original shape of the replaced portion. The method further includes coupling the replacement coupon to the parent component to form the secondary component. The method also includes at least one of (i) removing the replacement coupon from a build plate of the additive manufacturing system prior to application of any heat treatment to the as-built replacement coupon, wherein the replacement coupon maintains a near-net original shape of the replaced portion after removal, and (ii) entering the secondary component into normal duty with no hot isostatic press treatment of the replacement coupon having been performed.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: January 18, 2022
    Assignee: General Electric Company
    Inventors: Dheepa Srinivasan, Joydeep Pal, M. Raghunandan, Rohit Sen, Sridhar Balaram, Mohamed Aleem
  • Publication number: 20180130712
    Abstract: Methods for forming fins with a straight profile by preventing fin bending during STI fill and annealing are disclosed. Embodiments include providing STI regions separated by Si regions, each topped with a hardmask; planarizing the STI regions; removing the hardmask over a portion of the Si regions, forming recesses; forming a conformal spacer layer over the STI regions and in the recesses; removing horizontal portions of the spacer layer; epitaxially growing Si in each recess, forming fins; and etching the STI regions and a remainder of the spacer layer down to the Si regions to reveal the fins.
    Type: Application
    Filed: December 12, 2017
    Publication date: May 10, 2018
    Inventors: Ryan SPORER, Rohit PAL, Jeremy WAHL
  • Patent number: 9875936
    Abstract: Methods for forming fins with a straight profile by preventing fin bending during STI fill and annealing are disclosed. Embodiments include providing STI regions separated by Si regions, each topped with a hardmask; planarizing the STI regions; removing the hardmask over a portion of the Si regions, forming recesses; forming a conformal spacer layer over the STI regions and in the recesses; removing horizontal portions of the spacer layer; epitaxially growing Si in each recess, forming fins; and etching the STI regions and a remainder of the spacer layer down to the Si regions to reveal the fins.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: January 23, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ryan Sporer, Rohit Pal, Jeremy Wahl
  • Patent number: 9455201
    Abstract: In one aspect there is set forth herein a semiconductor device having a first field effect transistor formed in a substrate structure, and a second field effect transistor formed in the substrate structure. The first field effect transistor can include a first substrate structure doping, a first gate stack, and a first threshold voltage. The second field effect transistor can include the first substrate structure doping, a second gate stack different from the first gate stack, and a second threshold voltage different from the first threshold voltage.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: September 27, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Manoj Joshi, Manfred Eller, Rohit Pal, Richard J. Carter, Srikanth Balaji Samavedam, Bongki Lee, Jin Ping Liu
  • Patent number: 9362180
    Abstract: In one aspect there is set forth herein an integrated circuit having a first plurality of field effect transistors and a second plurality of field effect transistor, wherein field effect transistors of the first plurality of field effect transistors each have a first gate stack and wherein field effect transistors of the second plurality of field effect transistors each have a second gate stack, the second gate stack being different from the first gate stack by having a metal layer common to the first gate stack and the second gate stack that includes a first thickness at the first gate stack and a second thickness at the second gate stack.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: June 7, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Bongki Lee, Jin Ping Liu, Manoj Joshi, Manfred Eller, Rohit Pal, Richard J. Carter, Srikanth Balaji Samavedam
  • Patent number: 9362284
    Abstract: A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: June 7, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Mitsuhiro Togo, Changyong Xiao, Yiqun Liu, Dina H. Triyoso, Rohit Pal
  • Patent number: 9349814
    Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: May 24, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Tsung-Liang Chen, Hung-Wei Liu, Rohit Pal, Hsin-Neng Tai, Huey-Ming Wang, Tae Hoon Lee, Songkram Srivathanakul, Danni Chen
  • Publication number: 20160057302
    Abstract: In a method for scanning a book including a plurality of pages, a property of the plurality of pages is measured between a plurality of points on the top of the book and a plurality of points on the bottom of the book to generate a plurality of data values. The plurality of data values are grouped into a plurality of levels corresponding to the plurality of pages. A determination is made for each of the plurality of the points at each of the plurality of levels whether ink is present. Pixel data is generated, indicative of one of the presence or absence of ink at each of the plurality of points for each of the plurality of levels. An image is generated using the pixel data for each of the plurality of levels.
    Type: Application
    Filed: August 29, 2014
    Publication date: February 25, 2016
    Inventors: Vithi Mittal, Rohit Pal
  • Publication number: 20160049400
    Abstract: A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal.
    Type: Application
    Filed: October 27, 2015
    Publication date: February 18, 2016
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Mitsuhiro TOGO, Changyong XIAO, Yiqun LIU, Dina H. TRIYOSO, Rohit PAL
  • Publication number: 20150380409
    Abstract: A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal.
    Type: Application
    Filed: June 26, 2014
    Publication date: December 31, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Mitsuhiro TOGO, Changyong XIAO, Yiqun LIU, Dina H. TRIYOSO, Rohit PAL
  • Patent number: 9209186
    Abstract: A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: December 8, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mitsuhiro Togo, Changyong Xiao, Yiqun Liu, Dina H. Triyoso, Rohit Pal
  • Publication number: 20150311083
    Abstract: A method includes providing a gate structure having a dummy gate, a first spacer along a side of the gate. The dummy gate and the spacer are removed to expose a gate dielectric. A second spacer is deposited on at least one side of a gate structure cavity and a top of the gate dielectric. A bottom portion of the second spacer is removed to expose the gate dielectric and the gate structure is wet cleaned.
    Type: Application
    Filed: April 23, 2014
    Publication date: October 29, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Changyong XIAO, Hoong Shing WONG, Deepasree KONDUPARTHI, Rohit PAL
  • Patent number: 9157551
    Abstract: A microactuator may be configured by activating a source of electromagnetic radiation to heat and melt a selected set of phase-change plugs embedded in a substrate of the microactuator, pressurizing a common pressure chamber adjacent to each of the plugs to deform the melted plugs, and deactivating the source of electromagnetic radiation to cool and solidify the melted plugs.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: October 13, 2015
    Assignee: The Regents of the University of Michigan
    Inventors: Zhishan Hua, Erdogan Gulari, Mark A. Burns, Rohit Pal, Onnop Srivannavit
  • Patent number: 9159567
    Abstract: A method includes providing a gate structure having a dummy gate, a first spacer along a side of the gate. The dummy gate and the spacer are removed to expose a gate dielectric. A second spacer is deposited on at least one side of a gate structure cavity and a top of the gate dielectric. A bottom portion of the second spacer is removed to expose the gate dielectric and the gate structure is wet cleaned.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: October 13, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Changyong Xiao, Hoong Shing Wong, Deepasree Konduparthi, Rohit Pal
  • Publication number: 20150270364
    Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.
    Type: Application
    Filed: June 4, 2015
    Publication date: September 24, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Tsung-Liang CHEN, Hung-Wei LIU, Rohit PAL, Hsin-Neng TAI, Huey-Ming WANG, Tae Hoon LEE, Songkram SRIVATHANAKUL, Danni CHEN
  • Publication number: 20150243563
    Abstract: In one aspect there is set forth herein an integrated circuit having a first plurality of field effect transistors and a second plurality of field effect transistor, wherein field effect transistors of the first plurality of field effect transistors each have a first gate stack and wherein field effect transistors of the second plurality of field effect transistors each have a second gate stack, the second gate stack being different from the first gate stack by having a metal layer common to the first gate stack and the second gate stack that includes a first thickness at the first gate stack and a second thickness at the second gate stack.
    Type: Application
    Filed: February 25, 2014
    Publication date: August 27, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Bongki LEE, Jin Ping LIU, Manoj JOSHI, Manfred ELLER, Rohit PAL, Richard J. CARTER, Srikanth Balaji SAMAVEDAM
  • Publication number: 20150243652
    Abstract: In one aspect there is set forth herein a semiconductor device having a first field effect transistor formed in a substrate structure, and a second field effect transistor formed in the substrate structure. The first field effect transistor can include a first substrate structure doping, a first gate stack, and a first threshold voltage. The second field effect transistor can include the first substrate structure doping, a second gate stack different from the first gate stack, and a second threshold voltage different from the first threshold voltage.
    Type: Application
    Filed: February 25, 2014
    Publication date: August 27, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Manoj JOSHI, Manfred ELLER, Rohit PAL, Richard J. CARTER, Srikanth Balaji SAMAVEDAM, Bongki LEE, Jin Ping LIU
  • Patent number: 9093560
    Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: July 28, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Tsung-Liang Chen, Hung-Wei Liu, Rohit Pal, Hsin-Neng Tai, Huey-Ming Wang, Tae Hoon Lee, Songkram Srivathanakul, Danni Chen
  • Publication number: 20150084131
    Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.
    Type: Application
    Filed: September 20, 2013
    Publication date: March 26, 2015
    Inventors: Tsung-Liang CHEN, Hung-Wei LIU, Rohit PAL, Hsin-Neng TAI, Huey-Ming WANG, Tae Hoon LEE, Songkram SRIVATHANAKUL, Danni CHEN
  • Publication number: 20150055189
    Abstract: In a method for scanning a book including a plurality of pages, a property of the plurality of pages is measured between a plurality of points on the top of the book and a plurality of points on the bottom of the book to generate a plurality of data values. The plurality of data values are grouped into a plurality of levels corresponding to the plurality of pages. A determination is made for each of the plurality of the points at each of the plurality of levels whether ink is present. Pixel data is generated, indicative of one of the presence or absence of ink at each of the plurality of points for each of the plurality of levels. An image is generated using the pixel data for each of the plurality of levels.
    Type: Application
    Filed: August 25, 2014
    Publication date: February 26, 2015
    Inventors: Vithi Mittal, Rohit Pal