Abstract: Methods for forming fins with a straight profile by preventing fin bending during STI fill and annealing are disclosed. Embodiments include providing STI regions separated by Si regions, each topped with a hardmask; planarizing the STI regions; removing the hardmask over a portion of the Si regions, forming recesses; forming a conformal spacer layer over the STI regions and in the recesses; removing horizontal portions of the spacer layer; epitaxially growing Si in each recess, forming fins; and etching the STI regions and a remainder of the spacer layer down to the Si regions to reveal the fins.

Abstract: Methods for forming fins with a straight profile by preventing fin bending during STI fill and annealing are disclosed. Embodiments include providing STI regions separated by Si regions, each topped with a hardmask; planarizing the STI regions; removing the hardmask over a portion of the Si regions, forming recesses; forming a conformal spacer layer over the STI regions and in the recesses; removing horizontal portions of the spacer layer; epitaxially growing Si in each recess, forming fins; and etching the STI regions and a remainder of the spacer layer down to the Si regions to reveal the fins.

Abstract: In one aspect there is set forth herein a semiconductor device having a first field effect transistor formed in a substrate structure, and a second field effect transistor formed in the substrate structure. The first field effect transistor can include a first substrate structure doping, a first gate stack, and a first threshold voltage. The second field effect transistor can include the first substrate structure doping, a second gate stack different from the first gate stack, and a second threshold voltage different from the first threshold voltage.

Abstract: A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal.

Abstract: In one aspect there is set forth herein an integrated circuit having a first plurality of field effect transistors and a second plurality of field effect transistor, wherein field effect transistors of the first plurality of field effect transistors each have a first gate stack and wherein field effect transistors of the second plurality of field effect transistors each have a second gate stack, the second gate stack being different from the first gate stack by having a metal layer common to the first gate stack and the second gate stack that includes a first thickness at the first gate stack and a second thickness at the second gate stack.

Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.

Abstract: In a method for scanning a book including a plurality of pages, a property of the plurality of pages is measured between a plurality of points on the top of the book and a plurality of points on the bottom of the book to generate a plurality of data values. The plurality of data values are grouped into a plurality of levels corresponding to the plurality of pages. A determination is made for each of the plurality of the points at each of the plurality of levels whether ink is present. Pixel data is generated, indicative of one of the presence or absence of ink at each of the plurality of points for each of the plurality of levels. An image is generated using the pixel data for each of the plurality of levels.

Abstract: A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal.

Abstract: A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal.

Abstract: A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal.

Abstract: A method includes providing a gate structure having a dummy gate, a first spacer along a side of the gate. The dummy gate and the spacer are removed to expose a gate dielectric. A second spacer is deposited on at least one side of a gate structure cavity and a top of the gate dielectric. A bottom portion of the second spacer is removed to expose the gate dielectric and the gate structure is wet cleaned.

Abstract: A microactuator may be configured by activating a source of electromagnetic radiation to heat and melt a selected set of phase-change plugs embedded in a substrate of the microactuator, pressurizing a common pressure chamber adjacent to each of the plugs to deform the melted plugs, and deactivating the source of electromagnetic radiation to cool and solidify the melted plugs.

Abstract: A method includes providing a gate structure having a dummy gate, a first spacer along a side of the gate. The dummy gate and the spacer are removed to expose a gate dielectric. A second spacer is deposited on at least one side of a gate structure cavity and a top of the gate dielectric. A bottom portion of the second spacer is removed to expose the gate dielectric and the gate structure is wet cleaned.

Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.

Abstract: In one aspect there is set forth herein an integrated circuit having a first plurality of field effect transistors and a second plurality of field effect transistor, wherein field effect transistors of the first plurality of field effect transistors each have a first gate stack and wherein field effect transistors of the second plurality of field effect transistors each have a second gate stack, the second gate stack being different from the first gate stack by having a metal layer common to the first gate stack and the second gate stack that includes a first thickness at the first gate stack and a second thickness at the second gate stack.

Abstract: In one aspect there is set forth herein a semiconductor device having a first field effect transistor formed in a substrate structure, and a second field effect transistor formed in the substrate structure. The first field effect transistor can include a first substrate structure doping, a first gate stack, and a first threshold voltage. The second field effect transistor can include the first substrate structure doping, a second gate stack different from the first gate stack, and a second threshold voltage different from the first threshold voltage.

Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.

Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.

Abstract: In a method for scanning a book including a plurality of pages, a property of the plurality of pages is measured between a plurality of points on the top of the book and a plurality of points on the bottom of the book to generate a plurality of data values. The plurality of data values are grouped into a plurality of levels corresponding to the plurality of pages. A determination is made for each of the plurality of the points at each of the plurality of levels whether ink is present. Pixel data is generated, indicative of one of the presence or absence of ink at each of the plurality of points for each of the plurality of levels. An image is generated using the pixel data for each of the plurality of levels.

Abstract: When forming sophisticated high-k metal gate electrode structures, the uniformity of the device characteristics may be enhanced by growing a threshold adjusting semiconductor alloy on the basis of a hard mask regime, which may result in a less pronounced surface topography, in particular in densely packed device areas. To this end, in some illustrative embodiments, a deposited hard mask material may be used for selectively providing an oxide mask of reduced thickness and superior uniformity.