Abstract: In one embodiment, an apparatus comprises a memory comprising a group of memory cells coupled to a wordline; and a controller configured to skip programming of one or more pages of the group of memory cells responsive to a sequential write operation; and program the one or more pages of the group of memory cells responsive to one or more random write commands.

Abstract: Error correction coding (ECC) mis-corrected reads, if undetected, result in silent data corruption of a non-volatile memory device. Overcoming ECC mis-corrected reads is based on a read signature of a result of reading a page in the non-volatile memory device. An ECC mis-correct logic counts the number of bits in the end-most buckets into which the bits of the result is divided. End-most buckets that are overpopulated or starved reveal a tell-tale read signature of an ECC mis-correct. The ECC mis-correct is likely to occur when the read reference voltage level used to read the page is shifted in one direction or another to an extreme amount that risks reading data from a different page. Detecting ECC mis-corrected reads can be used to overcome the ECC mis-corrects and mitigate silent data corruption.

Abstract: A method is described. The method includes performing the following on a flash memory chip: measuring a temperature of the flash memory chip; and, changing a program step size voltage of the flash memory chip because the temperature of the flash memory chip has changed.

Abstract: In one embodiment, an apparatus comprises a memory comprising a group of memory cells coupled to a wordline; and a controller configured to skip programming of one or more pages of the group of memory cells responsive to a sequential write operation; and program the one or more pages of the group of memory cells responsive to one or more random write commands.

Abstract: A memory device comprising a memory array; and controller circuitry to apply a first pass voltage to a first plurality of unselected wordlines of the memory array during a string current sensing phase; and reduce the first pass voltage applied to the first plurality of unselected wordlines during a multistrobe sensing phase that follows the string current sensing phase.

Abstract: A nonvolatile (NV) memory device includes an NV storage media and a storage controller to control access to the NV storage media. In response to a host read request, the storage controller can determine if the NV storage media is in a stable Vt (threshold voltage) state. If the NV storage media is in a stable Vt state, the storage controller can perform a reset read operation prior to servicing the host read request. A reset read is a read operation that does not produce data to send back to the host. The reset read operation is a dummy read that puts the NV storage media into a transient Vt state, which has lower risk of read disturb.

Abstract: A memory device comprising a memory array; and controller circuitry to apply a first pass voltage to a first plurality of unselected wordlines of the memory array during a string current sensing phase; and reduce the first pass voltage applied to the first plurality of unselected wordlines during a multistrobe sensing phase that follows the string current sensing phase.

Abstract: Provided are techniques for resuming storage die programming after power loss. In response to receipt of an indication of the power loss, data that was to be programmed to multi-level cell NAND blocks are copied to single level cell NAND blocks and a pulse number at which programming was interrupted is stored. In response to receipt of an indication to resume from the power loss, the data is copied from the single level cell NAND blocks to a page buffer, the pulse number is retrieved, and programming of the multi-level cell NAND blocks is resumed at the retrieved pulse number using the data in the page buffer.

Abstract: A memory programmer apparatus may include a first-level programmer to program a first-level cell portion of a multi-level memory in a first pass, a coarse programmer to coarse program a second-level cell portion of the multi-level memory in the first pass, wherein the second-level cell portion includes more levels than the first-level cell portion, and a fine programmer to fine program the second-level cell portion of the multi-level memory in a second pass from data programmed in the first-level cell portion in the first pass.

Abstract: A device has a M8XY6 layer in between a first conductive layer on the top and a second conductive layer on the bottom, wherein (i) M includes at least one element selected from the following: Cu, Ag, Li, and Zn, (ii) X includes at least one Group XIV element, and (iii) Y includes at least one Group XVI element. Another device has MaXbYc material contacted on opposite sides by respective layers of conductive material, wherein: (i) M includes at least one element selected from the following: Cu, Ag, Li, and Zn, (ii) X includes at least one Group XIV element, and (iii) Y includes at least one Group XVI element, and a is in the range of 48-60 atomic percent, b is in the range of 4-10 atomic percent, c is in the range of 30-45 atomic percent, and a+b+c is at least 90 atomic percent.

Abstract: A crystalline semiconductor Schottky barrier-like diode sandwiched between two conducting electrodes is in series with a memory element, a word line and a bit line, wherein the setup provides voltage margins greater than 1V and current densities greater than 5×106 A/cm2. This Schottky barrier-like diode can be fabricated under conditions compatible with low-temperature BEOL semiconductor processing, can supply high currents at low voltages, exhibits high on-off ratios, and enables large memory arrays.

Abstract: A device for use with a memory cross-point array of elements, each of which comprises a selection device in series with a state-holding device, in one embodiment includes a controller, configured to apply at least one voltage and/or current pulse to a selected one or more of the elements, said selected one or more of the elements including a partially- or completely-shorted selection device, so that said partially- or completely-shorted selection device passes enough current so as to damage its corresponding state-holding device and place said corresponding state-holding device in a highly resistive state, while any other selection device that is not partially- or completely-shorted passes less current so that the state-holding device corresponding to said other selection device remains unaffected. Additional systems and methods are also presented.

Abstract: A system, method and computer program product produce spike-dependent plasticity in an artificial synapse. A method includes: an electronic device generating a pre-synaptic pulse that occurs a predetermined period of time after receiving a pre-synaptic spike at a first input. The electronic device generating a post-synaptic pulse that starts at a baseline value and reaches a first voltage value a first period of time after receiving a post-synaptic spike at a second input, followed by a second voltage value a second period of time after the post synaptic spike, followed by a return to said baseline voltage a third period of time after the post-synaptic spike. The generated pre-synaptic pulse is applied to a pre-synaptic node of a synaptic device in series with a rectifying element that has a turn-on voltage based on a threshold. The generated post-synaptic pulse is applied to a post-synaptic node of said synaptic device.

Abstract: A device for use with a memory cross-point array of elements, each of which comprises a selection device in series with a state-holding device, in one embodiment includes a controller, configured to apply at least one voltage and/or current pulse to a selected one or more of the elements, said selected one or more of the elements including a partially- or completely-shorted selection device, so that said partially- or completely-shorted selection device passes enough current so as to damage its corresponding state-holding device and place said corresponding state-holding device in a highly resistive state, while any other selection device that is not partially- or completely-shorted passes less current so that the state-holding device corresponding to said other selection device remains unaffected. Additional systems and methods are also presented.

Abstract: A crystalline semiconductor Schottky barrier-like diode sandwiched between two conducting electrodes is in series with a memory element, a word line and a bit line, wherein the setup provides voltage margins greater than 1V and current densities greater than 5×106 A/cm2. This Schottky barrier-like diode can be fabricated under conditions compatible with low-temperature BEOL semiconductor processing, can supply high currents at low voltages, exhibits high on-off ratios, and enables large memory arrays.

Abstract: A system, method and computer program product produce spike-dependent plasticity in an artificial synapse. A method includes: an electronic device generating a pre-synaptic pulse that occurs a predetermined period of time after receiving a pre-synaptic spike at a first input. The electronic device generating a post-synaptic pulse that starts at a baseline value and reaches a first voltage value a first period of time after receiving a post-synaptic spike at a second input, followed by a second voltage value a second period of time after the post synaptic spike, followed by a return to said baseline voltage a third period of time after the post-synaptic spike. The generated pre-synaptic pulse is applied to a pre-synaptic node of a synaptic device in series with a rectifying element that has a turn-on voltage based on a threshold. The generated post-synaptic pulse is applied to a post-synaptic node of said synaptic device.

Abstract: A device is disclosed having a M8XY6 layer sandwiched in between a first conductive layer on the top and a second conductive layer on the bottom, wherein (i) M includes at least one element selected from the group consisting of Cu, Ag, Li, and Zn, (ii) X includes at least one Group XIV element, and (iii) Y includes at least one Group XVI element. Also disclosed is a device comprising: an MaXbYc material contacted on opposite sides by respective layers of conductive material, wherein: (i) M includes at least one element selected from the group consisting of Cu, Ag, Li, and Zn, (ii) X includes at least one Group XIV element, and (iii) Y includes at least one Group XVI element, and wherein a is in the range of 48-60 atomic percent, b is in the range of 4-10 atomic percent, c is in the range of 30-45 atomic percent, and a+b+c is at least 90 atomic percent.

Abstract: The present disclosure relates to a solid electrolyte device comprising an amorphous chalcogenide solid active electrolytic layer; first and second metallic layers. The amorphous chalcogenide solid active electrolytic layer is located between the first and second metallic layers. The amorphous chalcogenide solid active electrolytic layer is prepared by obtaining a solution of a hydrazine-based precursor to a metal chalcogenide; applying the solution onto a substrate; and thereafter annealing the precursor to convert the precursor to the amorphous metal chalcogenide. The present disclosure also relates to processes for fabricating the solid electrolyte device.

Abstract: According to embodiments of the invention, a system, method and computer program product producing spike-dependent plasticity in an artificial synapse.

Abstract: The present disclosure relates to a solid electrolyte device comprising an amorphous chalcogenide solid active electrolytic layer; first and second metallic layers. The amorphous chalcogenide solid active electrolytic layer is located between the first and second metallic layers. The amorphous chalcogenide solid active electrolytic layer is prepared by obtaining a solution of a hydrazine-based precursor to a metal chalcogenide; applying the solution onto a substrate; and thereafter annealing the precursor to convert the precursor to the amorphous metal chalcogenide. The present disclosure also relates to processes for fabricating the solid electrolyte device.