Patents by Inventor Rohit Sehgal
Rohit Sehgal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250045198Abstract: Provided is a memory device, a method and a system that includes a host in communication with a system memory having a driver that creates commands for writing and reading data, and the memory device in communication with the host that includes a memory array including a plurality of memory components, a device attached memory including a submission queue and a completion queue for receiving commands from the driver, and a device controller configure to communicate with the device attached memory, the host and the plurality of memory components, such that the device controller receives an interface or link from the driver indicative of commands being placed into the submission queue, and automatically executes any pending commands therein for completion.Type: ApplicationFiled: May 30, 2024Publication date: February 6, 2025Applicant: Micron Technology, Inc.Inventors: Rohit SEHGAL, Vishal TANNA, Eishan MIRAKHUR, Satheesh Babu MUTHUPANDI, Rajinikanth PANDURANGAN
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Publication number: 20240319896Abstract: Provided is a system comprising a first interface configured to receive first data from an external computing device, non-volatile memory operatively coupled to the first interface, and a second interface configured to communicate with a host computing device. The system also includes dynamic random-access memory (DRAM) operatively coupled to the second interface, a memory controller operatively coupled to the second interface and the DRAM and configured to control a transfer of information between the DRAM and the host computing device through the second interface, and processing circuitry at least configured to store the first data received through the first interface in the non-volatile memory.Type: ApplicationFiled: March 7, 2024Publication date: September 26, 2024Applicant: Micron Technology, Inc.Inventors: Rohit SEHGAL, Vishal TANNA, Krishna SIDDHAREDDY, Eishan MIRAKHUR
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Publication number: 20240319880Abstract: Provided is a system comprising a first interface configured to receive first data from an external computing device, non-volatile memory operatively coupled to the first interface, and a second interface configured to communicate with a host computing device. The system also includes dynamic random-access memory (DRAM) operatively coupled to the second interface, a memory controller operatively coupled to the second interface and the DRAM and configured to control a transfer of information between the DRAM and the host computing device through the second interface, and processing circuitry at least configured to store the first data received through the first interface in the non-volatile memory.Type: ApplicationFiled: March 7, 2024Publication date: September 26, 2024Applicant: Micron Technology, Inc.Inventors: Rohit SEHGAL, Vishal TANNA, Krishna SIDDHAREDDY, Eishan MIRAKHUR
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Publication number: 20240311019Abstract: A system can include a first memory device including a persistent byte-addressable memory; a second memory device; and a processing device, operatively coupled with the first and second memory devices, to perform operations including: receiving a first host command to write or read user data; storing the user data in the persistent byte-addressable memory with a first data granularity; and transmitting the user data stored in the persistent byte-addressable memory to the second memory device. The operations can further include: responsive to determining that a power loss event has occurred during an operation to a particular data packet in a size of the first data granularity in the persistent byte-addressable memory, determining whether the first host command associated with the particular data packet is completely executed; and responsive to determining that the first host command is not completely executed, restoring the particular data packet in the persistent byte-addressable memory.Type: ApplicationFiled: February 26, 2024Publication date: September 19, 2024Inventors: Rohit Sehgal, Vishal Tanna, Eishan Mirakhur
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Patent number: 11943374Abstract: Described are a system, method, and computer program product for detecting malicious changelog modifications with blockchain. The method includes identifying at least one database transaction that was initiated in response to a request by a user and receiving a first changelog record associated with the at least one database transaction from a target blockchain of at least one changelog blockchain. The method also includes determining a public key associated with the user and attempting a decryption of the first changelog record using the public key. The method further includes detecting tampering of the target blockchain for the at least one database transaction based on determining that the decryption of the first changelog record has failed, and restoring at least part of the target blockchain with at least part of a verified changelog blockchain based on the tampering of the target blockchain.Type: GrantFiled: July 5, 2022Date of Patent: March 26, 2024Assignee: Visa International Service AssociationInventor: Rohit Sehgal
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Patent number: 11727984Abstract: Data storage devices, such as solid state drives (SSDs), are disclosed. A read threshold calibration operation is utilized to generate a calibrated read threshold for one or more voltage states of a cell of a MLC memory. A single-level cell (SLC) read is then executed to sense the ratio of bit values at the read thresholds of the voltage states, where SLC read refers to reading at a single read threshold, rather than to the cell type. The sensing results in a binary page with certain statistics of 1's and 0's. The ratio of 1's (or 0's) in the binary page is used to determine a deviation from the expected ratio, where the deviation is used to adjust the calibrated read threshold to match the voltage states of the MLC memory.Type: GrantFiled: February 24, 2021Date of Patent: August 15, 2023Assignee: Western Digital Technologies, Inc.Inventors: Eran Sharon, Karin Inbar, Alexander Bazarsky, Dudy David Avraham, Rohit Sehgal, Gilad Koren
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Patent number: 11722900Abstract: A method is disclosed. The method includes providing, by an SDK and a first application in a mobile device, first and second security values to a security value verification module in the mobile device. If the mobile device confirms that the first and second security values match, then a second application can proceed with interaction processing.Type: GrantFiled: August 31, 2021Date of Patent: August 8, 2023Assignee: Visa International Service AssociationInventors: Digvijay Goutam, Rohit Sehgal
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Publication number: 20230236742Abstract: A memory card, for use with a host system, combines both: (i) non-volatile memory express (NVMe) data storage such as a solid state drive (SSD) with (ii) dynamic random access memory (DRAM) conforming to the computer express link (CXL) protocol. The SSD and CXL DRAM share a common controller. CXL memory requests from the host system are handled according to the CXL.io protocol. NVMe data requests are wrapped into a CXL request packet. The common front end identifies the NVMe data request(s) within the CXL packet, parses the NVMe data request, and routes the request to the NVMe memory. A host operating system software driver intercepts the NVMe memory requests and wraps them into the CXL request packet.Type: ApplicationFiled: September 9, 2022Publication date: July 27, 2023Applicant: Micron Technology, Inc.Inventors: Rohit SEHGAL, Eishan MIRAKHUR, Vishal TANNA, Rohit SINDHU
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Publication number: 20230069097Abstract: A method is disclosed. The method includes providing, by an SDK and a first application in a mobile device, first and second security values to a security value verification module in the mobile device. If the mobile device confirms that the first and second security values match, then a second application can proceed with interaction processing.Type: ApplicationFiled: August 31, 2021Publication date: March 2, 2023Inventors: Digvijay Goutam, Rohit Sehgal
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Publication number: 20220337433Abstract: Described are a system, method, and computer program product for detecting malicious changelog modifications with blockchain. The method includes identifying at least one database transaction that was initiated in response to a request by a user and receiving a first changelog record associated with the at least one database transaction from a target blockchain of at least one changelog blockchain. The method also includes determining a public key associated with the user and attempting a decryption of the first changelog record using the public key. The method further includes detecting tampering of the target blockchain for the at least one database transaction based on determining that the decryption of the first changelog record has failed, and restoring at least part of the target blockchain with at least part of a verified changelog blockchain based on the tampering of the target blockchain.Type: ApplicationFiled: July 5, 2022Publication date: October 20, 2022Inventor: Rohit Sehgal
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Patent number: 11411745Abstract: Described are a system, method, and computer program product for detecting malicious changelog modifications with blockchain. The method includes receiving, from a computing device of a user, a request for a database transaction. The method also includes determining transaction-operative data associated with the database transaction and a user identifier. The method further includes generating an encrypted transaction record including the transaction-operative data and the user identifier. The method further includes broadcasting the encrypted transaction record to a changelog blockchain and, in response to receiving a confirmation of publication as a changelog record, initiating the database transaction. The method further includes receiving a verification request and the changelog record from a target blockchain.Type: GrantFiled: February 26, 2020Date of Patent: August 9, 2022Assignee: Visa International Service AssociationInventor: Rohit Sehgal
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Patent number: 11398288Abstract: A data storage system includes a storage medium and a storage controller configured to perform interface training operations. The interface training operations include loading a test data pattern into a first controller buffer of the storage controller, loading the test data pattern into a first storage medium buffer of the storage medium, setting a first read voltage or timing parameter at the storage controller, transferring the test data pattern from the first storage medium buffer to a second controller buffer of the storage controller using the first read voltage or timing parameter, comparing the test data pattern in the first controller buffer with the test data pattern in the second controller buffer, and determining a first read transfer error rate based on the first comparison.Type: GrantFiled: May 21, 2021Date of Patent: July 26, 2022Assignee: SANDISK TECHNOLOGIES LLCInventors: Phil Reusswig, Sahil Sharma, Rohit Sehgal, Niles Yang
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Publication number: 20220199156Abstract: The present disclosure generally relates to data storage devices, such as solid state drives (SSDs). A read threshold calibration operation is utilized to generate a calibrated read threshold for one or more voltage states of a cell of a MLC memory. A single-level cell (SLC) read is then executed to sense the ratio of bit values at the read thresholds of the voltage states, where SLC read refers to reading at a single read threshold, rather than to the cell type. The sensing results in a binary page with certain statistics of 1's and 0's. The ratio of 1's (or 0's) in the binary page is used to determine a deviation from the expected ratio, where the deviation is used to adjust the calibrated read threshold to match the voltage states of the MLC memory.Type: ApplicationFiled: February 24, 2021Publication date: June 23, 2022Inventors: Eran SHARON, Karin INBAR, Alexander BAZARSKY, Dudy David AVRAHAM, Rohit SEHGAL, Gilad KOREN
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Patent number: 11354190Abstract: Methods and apparatus for storing parity bits in an available over provisioning (OP) space to recover data lost from an entire memory block. For example, a data storage device may receive data from a host device, write the data to a block, and generate a corresponding block parity. The device may then determine a bit error rate (BER) of the block and an average programming duration to write the data written to the block, calculate a probability of the block becoming defective based on the BER and the average programming duration, and comparing the probability of the block to a set of probabilities respectively corresponding to a set of worst-performing blocks in a NVM. Thereafter, the device may write the block parity to an available over provisioning (OP) space in the NVM responsive to the probability of the block being greater than any probability in the set of probabilities.Type: GrantFiled: February 24, 2021Date of Patent: June 7, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Rohit Sehgal, Sahil Sharma, Nian Niles Yang, Philip David Reusswig
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Patent number: 11334256Abstract: A storage system and method for boundary wordline data retention handling are provided. In one embodiment, the storage system includes a memory having a single-level cell (SLC) block and a multi-level cell (MLC) block. The system determines if the boundary wordline in the MLC block has a data retention problem (e.g., by determining how long it has been since the boundary wordline was programmed). To address the data retention problem, the storage system can copy data from a wordline in the SLC block that corresponds to the boundary wordline in the MLC block to a wordline in another SLC block prior to de-committing the data in the SLC block. Alternatively, the storage system can reprogram the data in the boundary wordline using a double fine programing technique.Type: GrantFiled: February 3, 2020Date of Patent: May 17, 2022Assignee: Western Digital Technologies, Inc.Inventors: Sahil Sharma, Nian Niles Yang, Phil Reusswig, Rohit Sehgal, Piyush A. Dhotre
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Publication number: 20220050747Abstract: Methods and apparatus for storing parity bits in an available over provisioning (OP) space to recover data lost from an entire memory block. For example, a data storage device may receive data from a host device, write the data to a block, and generate a corresponding block parity. The device may then determine a bit error rate (BER) of the block and an average programming duration to write the data written to the block, calculate a probability of the block becoming defective based on the BER and the average programming duration, and comparing the probability of the block to a set of probabilities respectively corresponding to a set of worst-performing blocks in a NVM. Thereafter, the device may write the block parity to an available over provisioning (OP) space in the NVM responsive to the probability of the block being greater than any probability in the set of probabilities.Type: ApplicationFiled: February 24, 2021Publication date: February 17, 2022Inventors: Rohit Sehgal, Sahil Sharma, Nian Niles Yang, Philip David Reusswig
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Patent number: 11210001Abstract: Systems and methods for storage systems using storage device monitoring for load balancing are described. Storage devices may be configured for data access through a common data stream, such as the storage devices in a storage node or server. Data operations from the common data stream may be distributed among the storage devices using a load balancing algorithm. Performance parameter values, such as grown bad blocks, program-erase cycles, and temperature, may be received for the storage devices and used to determine variance values for each storage device. Variance values demonstrating degrading storage devices may be used to reduce the load allocation of data operations to the degrading storage devices.Type: GrantFiled: April 22, 2020Date of Patent: December 28, 2021Assignee: Western Digital Technologies, Inc.Inventors: Niles Yang, Phil Reusswig, Sahil Sharma, Rohit Sehgal
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Patent number: 11164634Abstract: A storage system comprises a controller connected to blocks of non-volatile memory cells. The memory cells can be operated as single level cell (“SLC”) memory cells or multi-level cell (“MLC”) memory cells. To increase write performance for a subset of memory cells being operated as SLC memory cells, the controller performs a deeper erase process and a weaker program process for the subset of memory cells. The weaker program process results in a programmed threshold voltage distribution that is lower than the “nominal” programmed threshold voltage distribution. Having a lower programmed threshold voltage distribution reduces the magnitude of the programming and sensing voltages needed and, therefore, shortens the time required to generate the programming and sensing voltages, and reduces power consumption.Type: GrantFiled: June 24, 2019Date of Patent: November 2, 2021Assignee: Western Digital Technologies, Inc.Inventors: Niles Yang, Sahil Sharma, Rohit Sehgal, Phil Reusswig
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Publication number: 20210334030Abstract: Systems and methods for storage systems using storage device monitoring for load balancing are described. Storage devices may be configured for data access through a common data stream, such as the storage devices in a storage node or server. Data operations from the common data stream may be distributed among the storage devices using a load balancing algorithm. Performance parameter values, such as grown bad blocks, program-erase cycles, and temperature, may be received for the storage devices and used to determine variance values for each storage device. Variance values demonstrating degrading storage devices may be used to reduce the load allocation of data operations to the degrading storage devices.Type: ApplicationFiled: April 22, 2020Publication date: October 28, 2021Inventors: Niles Yang, Phil Reusswig, Sahil Sharma, Rohit Sehgal
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Publication number: 20210266180Abstract: Described are a system, method, and computer program product for detecting malicious changelog modifications with blockchain. The method includes receiving, from a computing device of a user, a request for a database transaction. The method also includes determining transaction-operative data associated with the database transaction and a user identifier. The method further includes generating an encrypted transaction record including the transaction-operative data and the user identifier. The method further includes broadcasting the encrypted transaction record to a changelog blockchain and, in response to receiving a confirmation of publication as a changelog record, initiating the database transaction. The method further includes receiving a verification request and the changelog record from a target blockchain.Type: ApplicationFiled: February 26, 2020Publication date: August 26, 2021Inventor: Rohit Sehgal