Abstract: Systems and methods for storage systems using storage device monitoring for load balancing are described. Storage devices may be configured for data access through a common data stream, such as the storage devices in a storage node or server. Data operations from the common data stream may be distributed among the storage devices using a load balancing algorithm. Performance parameter values, such as grown bad blocks, program-erase cycles, and temperature, may be received for the storage devices and used to determine variance values for each storage device. Variance values demonstrating degrading storage devices may be used to reduce the load allocation of data operations to the degrading storage devices.

Abstract: Described are a system, method, and computer program product for detecting malicious changelog modifications with blockchain. The method includes receiving, from a computing device of a user, a request for a database transaction. The method also includes determining transaction-operative data associated with the database transaction and a user identifier. The method further includes generating an encrypted transaction record including the transaction-operative data and the user identifier. The method further includes broadcasting the encrypted transaction record to a changelog blockchain and, in response to receiving a confirmation of publication as a changelog record, initiating the database transaction. The method further includes receiving a verification request and the changelog record from a target blockchain.

Abstract: A storage system and method for boundary wordline data retention handling are provided. In one embodiment, the storage system includes a memory having a single-level cell (SLC) block and a multi-level cell (MLC) block. The system determines if the boundary wordline in the MLC block has a data retention problem (e.g., by determining how long it has been since the boundary wordline was programmed). To address the data retention problem, the storage system can copy data from a wordline in the SLC block that corresponds to the boundary wordline in the MLC block to a wordline in another SLC block prior to de-committing the data in the SLC block. Alternatively, the storage system can reprogram the data in the boundary wordline using a double fine programing technique.

Abstract: A method of operating a storage device, including; performing, by a non-volatile memory, an erase operation on a block of memory in the non-volatile memory, where the non-volatile memory is coupled to a controller; receiving, by the non-volatile memory, a host-transaction within a first time period, where, the non-volatile memory is coupled to a host device; and suspending, by the non-volatile memory, an erase operation in response to receiving the host-transaction by: determining the erase operation has completed a charge phase; and suspending the erase operation during a pulse phase of the erase operation. The method additionally includes the non-volatile memory maintaining a loop counter and a pulse counter, where: the loop counter increments in response to completion of an erase loop, and the pulse counter increments in response to completion of an erase pulse, where the erase pulse is applied during a pulse phase of the erase operation.

Abstract: A method of operating a storage device, including; performing, by a non-volatile memory, an erase operation on a block of memory in the non-volatile memory, where the non-volatile memory is coupled to a controller; receiving, by the non-volatile memory, a host-transaction within a first time period, where, the non-volatile memory is coupled to a host device; and suspending, by the non-volatile memory, an erase operation in response to receiving the host-transaction by: determining the erase operation has completed a charge phase; and suspending the erase operation during a pulse phase of the erase operation. The method additionally includes the non-volatile memory maintaining a loop counter and a pulse counter, where: the loop counter increments in response to completion of an erase loop, and the pulse counter increments in response to completion of an erase pulse, where the erase pulse is applied during a pulse phase of the erase operation.

Abstract: Preparing a key block in a memory system. Various methods include: selecting a candidate key block of memory; checking a quality of the candidate key block using a word line of the candidate key block; altering operating parameters of the candidate key memory block; and registering the candidate key memory block as the key block. Where altering the operating parameters includes replacing a first set of parameters associated with the first memory block with a second set of parameters, where the first set of parameters includes a first erase parameter, a first program parameter, and a first read parameter, where the memory block operating in a normal block mode is accessed using the first set of parameters, and the second set of parameters includes a second erase parameter, a second program parameter, and a second read parameter, where the first memory block is accessed using the second set of parameters.

Abstract: A system and method for a power-cycle based read scrub of a memory device is provided. A controller stores an access counter which indicates a number of times a logical block address (LBA) has been accessed. When the LBA is accessed, the LBA counter is incremented. If the LBA counter indicates a count higher than a predetermined count, data stored in the LBA is duplicated and the duplicate data is stored as backup data. Subsequent access of the LBA will show that the LBA count is higher than the predetermined count, so the backup data will be accessed rather than the original LBA, thus preventing read-induced failure of the data which may be caused by further repeated access of the same LBA.

Abstract: A data storage system performs operations including determining an endurance level of a block of memory cells; adjusting a read performance profile for the block of memory cells based on the determined endurance level; receiving a data read command specifying data to be read from a particular memory cell of the block of memory cells; and in response to the data read command, performing a read operation on the particular memory cell using the adjusted read performance profile.

Abstract: Techniques are described for performing a read scan process on a non-volatile memory system in order to determine memory blocks that may have a high bit error rate, where if such blocks are found they can be refreshed. Rather than work through the blocks of a memory system sequentially based on the physical block addresses, the memory system maintains a measure of data quality, such as an estimated or average bit error rate, for multi-block groups. For example, the groups can correspond to regions of memory die in the system. The groups are ranked by their data quality, with the groups being scanned in order of the data quality. The blocks within a group can also be ranked, based on factors such as the program/erase count.

Abstract: A storage system comprises a controller connected to blocks of non-volatile memory cells. The memory cells can be operated as single level cell (“SLC”) memory cells or multi-level cell (“MLC”) memory cells. To increase write performance for a subset of memory cells being operated as SLC memory cells, the controller performs a deeper erase process and a weaker program process for the subset of memory cells. The weaker program process results in a programmed threshold voltage distribution that is lower than the “nominal” programmed threshold voltage distribution. Having a lower programmed threshold voltage distribution reduces the magnitude of the programming and sensing voltages needed and, therefore, shortens the time required to generate the programming and sensing voltages, and reduces power consumption.

Abstract: A data storage system performs operations including determining an endurance level of a block of memory cells; adjusting a read performance profile for the block of memory cells based on the determined endurance level; receiving a data read command specifying data to be read from a particular memory cell of the block of memory cells; and in response to the data read command, performing a read operation on the particular memory cell using the adjusted read performance profile.

Abstract: A Data Storage Device (DSD) or a server is set to an unlocked state to allow access to a memory of the DSD or to a DSD of the server. Communication is established with an access station using a wireless communication interface, and an access code is received from the access station via the wireless communication interface. If the received access code is determined to be valid, the DSD or server is set to the unlocked state. According to another aspect, communication is established with a DSD or a server using a wireless communication interface, and an access code is generated and sent to the DSD or the server for setting the DSD or the server to the unlocked state.

Abstract: In one embodiment, there is a method for implementing balancing block wearing leveling at a storage device including one or more single level cell (SLC) blocks in a SLC block pool and one or more non-single level cell (nSLC) blocks in a nSLC block pool for storing data and a memory controller for performing operations on the SLC blocks and nSLC blocks, the method comprising: at the memory controller: receiving a first request to perform a wear leveling operation on a respective block pool of one of: the SLC block pool and the nSLC block pool; determining whether one or more blocks in the respective block pool meet block pool transfer criteria; in response to a determination that the one or more blocks in the respective block pool meets block pool transfer criteria, reclassifying the one or more blocks in the respective block pool as the other of the SLC block pool and the nSLC block pool; and in response to a determination that the one or more blocks in the respective block pool does not meet block pool trans

Abstract: Detecting a faulty memory block. Various methods include: performing a read operation on a memory block of the memory array, the read operation generates a failed bit count; determining the failed bit count in above a value associated with an overall failed bit count; determining the failed bit count is above a threshold value; in response, performing a confirmation process on the memory block, the confirmation process defining a number of consecutive erase cycles and a level of an erase cycle, the confirmation process results in erase pass or erase fail; and marking the memory block for garbage collection in response to determining the confirmation process results in erase fail. Methods additionally include setting the level of the erase cycle by modifying at least one selected form the group comprising: an erase voltage parameter; an erase verify parameter; and a number of bits ignored during the erase cycle.

Abstract: The present disclosure, in various embodiments, describes technologies and techniques for use by a memory controller or similar device for storing sequential image data or other data streams composed of pages of data. In one example, the memory controller compares data within current and previous image frames on a page-by-page basis. If a pair of pages match, the memory controller creates a link between the two pages so the duplicate page need not be stored. During a subsequent read operation, the flash controller accesses stored links to identify the physical storage addresses of any matching pages stored in connection with a previous frame to permit efficient retrieval. In some examples, a page is compared with both the previous corresponding page and with the neighboring pages of that previous page. Exemplary read, write and erase operations are described herein using the links.

Abstract: In one embodiment there is a method for calculating a timer at a storage device including a plurality of memory portions for storing data and a memory controller for performing operations on the memory portions, the method comprises receiving a request to perform an initial operation on a memory portion; determining an operational characteristic associated with the initial operation to be performed on the memory portion; and calculating an amount of time for a memory portion timer based on the operational characteristics before the initiation of the initial operation on the memory portion, wherein performance of a subsequent operation for another memory portion is delayed until the amount of time for the memory portion timer has elapsed since initiation of the operation on the memory portion.

Abstract: In one embodiment there is a method for calculating a timer at a storage device including a plurality of memory portions for storing data and a memory controller for performing operations on the memory portions, the method comprises receiving a request to perform an initial operation on a memory portion; determining an operational characteristic associated with the initial operation to be performed on the memory portion; and calculating an amount of time for a memory portion timer based on the operational characteristics before the initiation of the initial operation on the memory portion, wherein performance of a subsequent operation for another memory portion is delayed until the amount of time for the memory portion timer has elapsed since initiation of the operation on the memory portion.

Abstract: In one embodiment, there is a method for implementing balancing block wearing leveling at a storage device including one or more single level cell (SLC) blocks in a SLC block pool and one or more non-single level cell (nSLC) blocks in a nSLC block pool for storing data and a memory controller for performing operations on the SLC blocks and nSLC blocks, the method comprising: at the memory controller: receiving a first request to perform a wear leveling operation on a respective block pool of one of: the SLC block pool and the nSLC block pool; determining whether one or more blocks in the respective block pool meet block pool transfer criteria; in response to a determination that the one or more blocks in the respective block pool meets block pool transfer criteria, reclassifying the one or more blocks in the respective block pool as the other of the SLC block pool and the nSLC block pool; and in response to a determination that the one or more blocks in the respective block pool does not meet block pool trans

Abstract: Preparing a key block in a memory system. Various methods include: selecting a candidate key block of memory; checking a quality of the candidate key block using a word line of the candidate key block; altering operating parameters of the candidate key memory block; and registering the candidate key memory block as the key block. Where altering the operating parameters includes replacing a first set of parameters associated with the first memory block with a second set of parameters, where the first set of parameters includes a first erase parameter, a first program parameter, and a first read parameter, where the memory block operating in a normal block mode is accessed using the first set of parameters, and the second set of parameters includes a second erase parameter, a second program parameter, and a second read parameter, where the first memory block is accessed using the second set of parameters.

Abstract: A non-volatile memory system and corresponding method of operation are provided. The system includes non-volatile memory cells, each retaining a threshold voltage within a threshold window. The non-volatile memory cells include multi-bit cells each configured to store a plurality of bits of data with the threshold window partitioned into bands each having a band width. The bands include a lowest band denoting an erased state and increasing bands. A control circuit programs a first set of the data into the multi-bit cells in a single-bit mode using first target states being one of the erased state and a tight intermediate state having a distribution of the threshold voltage no wider than the band width of one of the increasing bands. The control circuit also programs a second set of the data into the multi-bit cells in a multi-bit mode with each of the multi-bit cells storing the plurality of bits.