Abstract: A method and system for measuring misregistration between different layers of a semiconductor device, the method including providing a set of pupil inaccuracy scalable basis elements (PISBEs) relating to a plurality of patterned semiconductor device wafers (PSDWs), generating a single pupil image of a site on a PSDW, the PSDW being one of the plurality of PSDWs, by taking a single measurement of the site, the single pupil image including a plurality of site-specific pixels, calculating a set of site-specific pupil inaccuracy scalable basis element scaling factors (PISBESFs) for the single pupil image using the set of PISBEs and the plurality of site-specific pixels and calculating a site-specific misregistration value (SSMV) using the set of PISBEs and the set of site-specific PISBESFs.

Abstract: A method for process control in the manufacture of semiconductor devices including performing metrology on at least one semiconductor wafer included in a given lot of semiconductor wafers, following processing of the at least one semiconductor wafer by a first processing step, generating, based on the metrology, at least one correctable to a second processing step subsequent to the processing step and adjusting, based on the correctable, performance of the second processing step on at least some semiconductor waters of the given lot of semiconductor wafers.

Abstract: A metrology system and metrology methods are disclosed. The metrology system comprises a set of device features on a first layer of a sample, a first set of target features on a second layer of the sample and overlapping the set of device features, and a second set of target features on the second layer of the sample and overlapping the set of device features. Relative positions of a first set of Moiré fringes and a second set of Moiré fringes indicate overlay error between the first layer of the sample and the second layer of the sample.

Abstract: A method of measuring misregistration in the manufacture of semiconductor devices including providing a multilayered semiconductor device, using a scatterometry metrology tool to perform misregistration measurements at multiple sites on the multilayered semiconductor device, receiving raw misregistration data for each of the misregistration measurements, thereafter providing filtered misregistration data by removing outlying raw misregistration data points from the raw misregistration data for each of the misregistration measurements, using the filtered misregistration data to model misregistration for the multilayered semiconductor device, calculating correctables from the modeled misregistration for the multilayered semiconductor device, providing the correctables to the scatterometry metrology tool, thereafter recalibrating the scatterometry metrology tool based on the correctables and measuring misregistration using the scatterometry metrology tool following the recalibration.

Abstract: A target and method for using the same in the measurement of misregistration between at least a first layer and a second layer formed on a wafer in the manufacture of functional semiconductor devices on the wafer, the functional semiconductor devices including functional device structures (FDSTs), the target including a plurality of measurement structures (MSTs), the plurality of MSTs being part of the first layer and the second layer and a plurality of device-like structures (DLSTs), the plurality of DLSTs being part of at least one of the first layer and the second layer, the DLSTs sharing at least one characteristic with the FDSTs and the MSTs not sharing the at least one characteristic with the FDSTs.

Abstract: A method for process control in the manufacture of semiconductor devices including performing metrology on at least one Design of Experiment (DOE) semiconductor wafer included in a lot of semiconductor wafers, the lot forming part of a batch of semiconductor wafer lots, generating, based on the metrology, one or more correctables to a process used to manufacture the lot of semiconductor wafers and adjusting, based on the correctables, the process performed on at least one of; other semiconductor wafers included in the lot of semi-conductor wafers, and other lots of semiconductor wafers included in the batch.

Abstract: A metrology system is disclosed, in accordance with one or more embodiments of the present disclosure. The metrology system includes a stage configured to secure a sample, one or more diffraction-based overlay (DBO) metrology targets disposed on the sample. The metrology system includes a light source and one or more sensors. The metrology system includes a set of optics configured to direct illumination light from the light source to the one or more DBO metrology targets of the sample, the set of optics including a half-wave plate, the half-wave plate selectively insertable into an optical path such that the half-wave plate selectively passes both illumination light from an illumination channel and collection light from a collection channel, the half-wave plate being configured to selectively align an orientation of linearly polarized illumination light from the light source to an orientation of a grating of the one or more DBO metrology targets.

Abstract: A misregistration measurement and region of interest selection system (MMRSS) for measuring misregistration between at least two layers on a wafer in the manufacture of semiconductor devices, the MMRSS including a set of misregistration metrology tools, including at least two misregistration metrology tools, and a misregistration analysis and region of interest selection engine operative to: analyze a plurality of misregistration measurement data sets associated with a set of regions of interest (ROIs) of at least one measurement site on the wafer and at least partially generated by at least one first misregistration metrology tool, and wherein each of the data sets is associated with a set of quality metrics, identify a recommended ROI and communicate the recommended ROI to at least one second misregistration metrology tool of the set of misregistration metrology tools, the second misregistration metrology tool being operative to generate misregistration metrology data associated with the recommended ROI.

Abstract: A multiple-tool parameter set calibration and misregistration measurement method useful in the manufacture of semiconductor devices including using at least a first reference misregistration metrology tool using a first set of measurement parameters to measure misregistration between at least two layers on a wafer of a batch of wafers, thereby generating a first misregistration data set, transmitting the first set of parameters and the data set to a calibrated set of measurement parameters generator (CSMPG) which processes the first set of parameters and the data set thereby generating a calibrated set of measurement parameters which are transmitted from the CSMPG to calibrate at least one initially-uncalibrated misregistration metrology tool based on the calibrated set of measurement parameters.

Abstract: A misregistration metrology system useful in manufacturing semiconductor device wafers including an optical misregistration metrology tool configured to measure misregistration at at least one target between two layers of a semiconductor device which is selected from a batch of semiconductor device wafers which are intended to be identical, an electron beam misregistration metrology tool configured to measure misregistration at the at least one target between two layers of a semiconductor device which is selected from the batch and a combiner operative to combine outputs of the optical misregistration metrology tool and the electron beam misregistration metrology tool to provide a combined misregistration metric.

Abstract: A system for analyzing one or more samples includes a sample analysis sub-system configured to perform one or more measurements on the one or more samples. The system further includes a controller configured to: receive design of experiment (DoE) data for performing the one or more measurements on the one or more samples; determine rankings for a set of target parameters; generate a recipe for performing the one or more measurements on the one or more samples based on the DoE data and the rankings of the set of target parameters; determine run parameters based on the recipe; perform the one or more measurements on the one or more samples, via the sample analysis sub-system, according to the recipe; and adjust the run parameters based on output data associated with performing the one or more measurements on the one or more samples.

Abstract: Targets, target elements and target design method are provided, which comprise designing a target structure to have a high contrast above a specific contrast threshold to its background in polarized light while having a low contrast below the specific contrast threshold to its background in non-polarized light. The targets may have details at device feature scale and be compatible with device design rules yet maintain optical contrast when measured with polarized illumination and thus be used effectively as metrology targets. Design variants and respective measurement optical systems are likewise provided.

Abstract: A metrology system may include a controller to receive a first metrology dataset associated with a first set of metrology target features on a sample including first features from a first exposure field on a first sample layer and second features from a second exposure field on a second sample layer, where the second exposure field partially overlaps the first exposure field. The controller may further receive a second metrology dataset associated with a second set of metrology target features including third features from a third exposure field on the second layer that overlaps the first exposure field and fourth features formed from a fourth exposure field on the first layer of the sample that overlaps the second exposure field. The controller may further determine fabrication errors based on the first and second metrology datasets and generate correctables to adjust a lithography tool based on the fabrication errors.

Abstract: A multiple-tool parameter set configuration and misregistration measurement system and method useful in the manufacture of semiconductor devices including using a first misregistration metrology tool using a first set of measurement parameters to measure misregistration between at least two layers at multiple sites on a wafer, including a plurality of semiconductor devices, the wafer being selected from a batch of wafers including a plurality of semiconductor devices intended to be identical to corresponding semiconductor devices on all other wafers in the batch of wafers, thereby generating a plurality of first misregistration data sets, using a second misregistration metrology tool using a second set of measurement parameters to measure misregistration between the at least two layers at multiple sites on a wafer selected from the batch of wafers, thereby generating a plurality of second misregistration data sets, selecting an adjusted first set of modeled measurement parameters associated with the first mis

Abstract: A metrology system includes a controller communicatively coupled to one or more metrology tools. In another embodiment, the controller includes one or more processors configured to execute program instructions causing the one or more processors to receive one or more overlay metrology measurements of one or more metrology targets of the metrology sample from the one or more metrology tools; determine tilt from the one or more measurement overlay measurements; and determine one or more correctables for at least one of one or more lithography tools or the one or more metrology tools to adjust for the tilt, where the one or more correctables are configured to reduce an amount of tilt in the sample or overlay inaccuracy of the one or more overlay metrology measurements. The program instructions further cause the one or more processors to predict tilt with a simulator based on at least the determined tilt.

Abstract: A method of measuring misregistration in the manufacture of semiconductor devices including providing a multilayered semiconductor device, using a scatterometry metrology tool to perform misregistration measurements at multiple sites on the multilayered semiconductor device, receiving raw misregistration data for each of the misregistration measurements, thereafter providing filtered misregistration data by removing outlying raw misregistration data points from the raw misregistration data for each of the misregistration measurements, using the filtered misregistration data to model misregistration for the multilayered semiconductor device, calculating correctables from the modeled misregistration for the multilayered semiconductor device, providing the correctables to the scatterometry metrology tool, thereafter recalibrating the scatterometry metrology tool based on the correctables and measuring misregistration using the scatterometry metrology tool following the recalibration.

Abstract: A metrology system may include a controller coupled to a metrology tool. The controller may receive a metrology target design including at least a first feature formed by exposing a first exposure field on a sample with a lithography tool, and at least a second feature formed by exposing a second exposure field on the sample with the lithography tool, where the second exposure field overlaps the first exposure field at a location of a metrology target on the sample. The controller may further receive metrology data associated with the metrology target fabricated according to the metrology target design, determine one or more fabrication errors during fabrication of the metrology target based on the metrology data, and generate correctables to adjust one or more fabrication parameters of the lithography tool in one or more subsequent lithography steps based on the one or more fabrication errors.

Abstract: Methods and metrology modules are provided, which derive landscape information (expressing relation(s) between metrology metric(s) and measurement parameters) from produced wafers, identifying therein indications for production process changes, and modify production process parameters with respect to the identified indications, to maintain the production process within specified requirements. Process changes may be detected in wafer(s), wafer lot(s) and batches, and the information may be used to detect root causes for the changes with respect to production tools and steps and to indicate tool aging and required maintenance. The information and its analysis may further be used to optimize the working point parameters, to optimizing designs of devices and/or targets and/or to train corresponding algorithms to perform the identifying, e.g., using training wafers.

Abstract: A method of measuring misregistration in the manufacture of semiconductor devices including providing a multilayered semiconductor device, using a scatterometry metrology tool to perform misregistration measurements at multiple sites on the multilayered semiconductor device, receiving raw misregistration data for each of the misregistration measurements, thereafter providing filtered misregistration data by removing outlying raw misregistration data points from the raw misregistration data for each of the misregistration measurements, using the filtered misregistration data to model misregistration for the multilayered semiconductor device, calculating correctables from the modeled misregistration for the multilayered semiconductor device, providing the correctables to the scatterometry metrology tool, thereafter recalibrating the scatterometry metrology tool based on the correctables and measuring misregistration using the scatterometry metrology tool following the recalibration.

Abstract: A multiple-tool parameter set configuration and misregistration measurement system and method useful in the manufacture of semiconductor devices including using a first misregistration metrology tool using a first set of measurement parameters to measure misregistration between at least two layers at multiple sites on a wafer, including a plurality of semiconductor devices, the wafer being selected from a batch of wafers including a plurality of semiconductor devices intended to be identical to corresponding semiconductor devices on all other wafers in the batch of wafers, thereby generating a plurality of first misregistration data sets, using a second misregistration metrology tool using a second set of measurement parameters to measure misregistration between the at least two layers at multiple sites on a wafer selected from the batch of wafers, thereby generating a plurality of second misregistration data sets, selecting an adjusted first set of modeled measurement parameters associated with the first mis