Patents by Inventor Roland Rupp

Roland Rupp has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11887894
    Abstract: A method for processing a wide band gap semiconductor wafer includes: depositing a support layer including semiconductor material at a back side of a wide band gap semiconductor wafer, the wide band gap semiconductor wafer having a band gap larger than the band gap of silicon; depositing an epitaxial layer at a front side of the wide band gap semiconductor wafer; and splitting the wide band gap semiconductor wafer along a splitting region to obtain a device wafer comprising at least a part of the epitaxial layer, and a remaining wafer comprising the support layer.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: January 30, 2024
    Assignee: Infineon Technologies AG
    Inventors: Francisco Javier Santos Rodriguez, Günter Denifl, Tobias Hoechbauer, Martin Huber, Wolfgang Lehnert, Roland Rupp, Hans-Joachim Schulze
  • Patent number: 11881397
    Abstract: A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: January 23, 2024
    Assignee: Infineon Technologies AG
    Inventors: Iris Moder, Bernhard Goller, Tobias Franz Wolfgang Hoechbauer, Roland Rupp, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
  • Patent number: 11881406
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a carbon structure on a handle substrate at a first surface of the handle substrate. The method further includes attaching a first surface of a semiconductor substrate to the first surface of the handle substrate. The method further includes processing the semiconductor substrate and performing a separation process to separate the handle substrate from the semiconductor substrate. The separation process comprises modifying the carbon structure.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: January 23, 2024
    Assignee: Infineon Technologies AG
    Inventors: Francisco Javier Santos Rodriguez, Roland Rupp, Hans-Joachim Schulze
  • Patent number: 11869840
    Abstract: A power semiconductor device includes a semiconductor substrate having a wide bandgap semiconductor material and a first surface, an insulation layer above the first surface of the semiconductor substrate, the insulation layer including at least one opening extending through the insulation layer in a vertical direction, a front metallization above the insulation layer with the insulation layer being interposed between the front metallization and the first surface of the semiconductor substrate, and a metal connection arranged in the opening of the insulation layer and electrically conductively connecting the front metallization with the semiconductor substrate; wherein the front metallization includes at least one layer that is a metal or a metal alloy having a higher melting temperature than an intrinsic temperature of the wide bandgap semiconductor material of the semiconductor substrate.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: January 9, 2024
    Assignee: Infineon Technologies AG
    Inventors: Ralf Siemieniec, Dethard Peters, Roland Rupp
  • Patent number: 11854926
    Abstract: A semiconductor device includes a semiconductor body comprising a first surface and an edge surface, a contact electrode formed on the first surface and comprising an outer edge side, and a passivation layer section conformally covering the outer edge side of the contact electrode. The passivation layer section is a multi-layer stack comprising a first layer, a second layer, and a third layer. Each of the first, second and third layers include outer edge sides facing the edge surface and opposite facing inner edge sides. The outer edge side of the contact electrode is disposed laterally between the inner edge sides and the outer edge sides of each layer.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: December 26, 2023
    Assignee: Infineon Technologies AG
    Inventors: Jens Peter Konrath, Christian Hecht, Roland Rupp, Andre Kabakow
  • Publication number: 20230411336
    Abstract: A semiconductor wafer includes: a first main surface and a second main surface opposite the first main surface; a detachment plane parallel to the first main surface inside the semiconductor wafer, the detachment plane defined by defects; electronic semiconductor components formed at the first main surface and between the first main surface and the detachment plane; and a glass structure attached to the first main surface. The glass structure includes openings, each of which leaves a respective area of the electronic semiconductor components uncovered. A method of processing the wafer, a clip, and a semiconductor device are also described.
    Type: Application
    Filed: August 3, 2023
    Publication date: December 21, 2023
    Inventors: Carsten von Koblinski, Daniel Pedone, Matteo Piccin, Roland Rupp, Chiew Li Tai, Jia Yi Wong
  • Publication number: 20230361196
    Abstract: A method includes: providing a layer of porous silicon carbide supported by a silicon carbide substrate; providing a layer of epitaxial silicon carbide on the layer of porous silicon carbide; forming semiconductor devices in the layer of epitaxial silicon carbide; and separating the silicon carbide substrate from the layer of epitaxial silicon carbide at the layer of porous silicon carbide. The layer of porous silicon carbide includes dopants defining a resistivity of the layer of porous silicon carbide. The resistivity of the layer of porous silicon carbide is different from a resistivity of the silicon carbide substrate. Additional methods are described.
    Type: Application
    Filed: July 13, 2023
    Publication date: November 9, 2023
    Inventors: Hans-Joachim Schulze, Roland Rupp, Francisco Javier Santos Rodriguez
  • Publication number: 20230330769
    Abstract: Provided is a machining apparatus including a profile sensor unit configured to obtain shape information about a parent substrate; and a laser scan unit configured to direct a laser beam onto the parent substrate, wherein a laser beam axis of the laser beam is tilted to an exposed main surface of the parent substrate, and wherein a track of the laser beam on the parent substrate is controllable as a function of the shape information obtained from the profile sensor unit.
    Type: Application
    Filed: June 16, 2023
    Publication date: October 19, 2023
    Inventors: Ralf Rieske, Alexander Binter, Wolfgang Diewald, Bernhard Goller, Heimo Graf, Gerald Lackner, Jan Richter, Roland Rupp, Guenter Schagerl, Marko David Swoboda
  • Publication number: 20230334337
    Abstract: A method for producing a silicon carbide component includes forming a silicon carbide layer on an initial wafer, wherein the silicon carbide layer comprises a doping region to be produced, forming an electrically conductive contact structure on the surface of the silicon carbide layer, the electrically conductive contact structure, producing a splitting region by pre-damaging the splitting region, wherein the splitting region is produced by laser treating the splitting region before forming the electrically conductive contact, splitting the silicon carbide layer or the initial wafer along the splitting region such that a silicon carbide substrate of the silicon carbide component to be produced is split off, wherein the silicon carbide substrate has a thickness of more than 30 µm, wherein the doping region extends to a surface of the silicon carbide layer before splitting the silicon carbide layer, and wherein splitting along comprises applying a polymer film.
    Type: Application
    Filed: June 12, 2023
    Publication date: October 19, 2023
    Inventors: Roland Rupp, Ronny Kern
  • Patent number: 11756917
    Abstract: A method for processing a semiconductor wafer is provided. A semiconductor wafer includes a first main surface and a second main surface. Defects are generated inside the semiconductor wafer to define a detachment plane parallel to the first main surface. Processing the first main surface defines a plurality of electronic semiconductor components. A glass structure is provided which includes a plurality of openings. The glass structure is attached to the processed first main surface, each of the plurality of openings leaving a respective area of the plurality of electronic semiconductor components uncovered. A polymer layer is applied to the second main surface and the semiconductor wafer is split into a semiconductor slice and a remaining semiconductor wafer by cooling the polymer layer beneath its glass transition temperature along the detachment plane. The semiconductor slice includes the plurality of electronic semiconductor components.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: September 12, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Carsten von Koblinski, Daniel Pedone, Matteo Piccin, Roland Rupp, Chiew Li Tai, Jia Yi Wong
  • Patent number: 11735642
    Abstract: A method includes providing a layer of porous silicon carbide supported by a silicon carbide substrate, providing a layer of epitaxial silicon carbide on the layer of porous silicon carbide, forming a plurality of semiconductor devices in the layer of epitaxial silicon carbide, and separating the substrate from the layer of epitaxial silicon carbide at the layer of porous silicon carbide. Additional methods are described.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: August 22, 2023
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Roland Rupp, Francisco Javier Santos Rodriguez
  • Patent number: 11721547
    Abstract: A method for manufacturing a silicon carbide substrate for an electrical silicon carbide device includes providing a silicon carbide dispenser wafer including a silicon face and a carbon face and depositing a silicon carbide epitaxial layer on the silicon face. Further, the method includes implanting ions with a predefined energy characteristic forming an implant zone within the epitaxial layer, so that the ions are implanted with an average depth within the epitaxial layer corresponding to a designated thickness of an epitaxial layer of the silicon carbide substrate to be manufactured. Furthermore, the method comprises bonding an acceptor wafer onto the epitaxial layer so that the epitaxial layer is arranged between the dispenser wafer and the acceptor wafer. Further, the epitaxial layer is split along the implant zone so that a silicon carbide substrate represented by the acceptor wafer with an epitaxial layer with the designated thickness is obtained.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 8, 2023
    Assignee: Infineon Technologies AG
    Inventors: Christian Hecht, Tobias Hoechbauer, Roland Rupp, Hans-Joachim Schulze
  • Patent number: 11712749
    Abstract: Provided is a parent substrate that includes a central region and an edge region. The edge region surrounds the central region. A detachment layer is formed in the central region. The detachment layer extends parallel to a main surface of the parent substrate. The detachment layer includes modified substrate material. A groove is formed in the edge region. The groove laterally encloses the central region. The groove runs vertically and/or tilted to the detachment layer.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: August 1, 2023
    Assignee: Infineon Technologies AG
    Inventors: Ralf Rieske, Alexander Binter, Wolfgang Diewald, Bernhard Goller, Heimo Graf, Gerald Lackner, Jan Richter, Roland Rupp, Guenter Schagerl, Marko Swoboda
  • Patent number: 11715768
    Abstract: A method for producing a silicon carbide component includes forming a silicon carbide layer on an initial wafer, forming a doping region of the silicon carbide component to be produced in the silicon carbide layer, and forming an electrically conductive contact structure of the silicon carbide component to be produced on a surface of the silicon carbide layer. The electrically conductive contact structure electrically contacts the doping region. Furthermore, the method includes splitting the silicon carbide layer or the initial wafer after forming the electrically conductive contact structure, such that a silicon carbide substrate at least of the silicon carbide component to be produced is split off.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: August 1, 2023
    Assignee: Infineon Technologies AG
    Inventors: Roland Rupp, Ronny Kern
  • Patent number: 11515264
    Abstract: A method for processing a semiconductor wafer is proposed. The method may include reducing a thickness of the semiconductor wafer. A carrier structure is placed on a first side of the semiconductor wafer, e.g. before or after reducing the thickness of the semiconductor wafer. The method further includes providing a support structure on a second side of the semiconductor wafer opposite to the first side, e.g. after reducing the thickness of the semiconductor wafer. Methods for welding a support structure onto a semiconductor wafer are proposed. Further, semiconductor composite structures with support structures welded onto a semiconductor wafer are proposed.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: November 29, 2022
    Assignee: Infineon Technologies AG
    Inventors: Francisco Javier Santos Rodriguez, Alexander Breymesser, Erich Griebl, Michael Knabl, Matthias Kuenle, Andreas Moser, Roland Rupp, Hans-Joachim Schulze, Sokratis Sgouridis, Stephan Voss
  • Publication number: 20220367191
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a carbon structure on a handle substrate at a first surface of the handle substrate. The method further includes attaching a first surface of a semiconductor substrate to the first surface of the handle substrate. The method further includes processing the semiconductor substrate and performing a separation process to separate the handle substrate from the semiconductor substrate. The separation process comprises modifying the carbon structure.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 17, 2022
    Inventors: Francisco Javier Santos Rodriguez, Roland Rupp, Hans-Joachim Schulze
  • Publication number: 20220359428
    Abstract: A method for processing a semiconductor wafer is proposed. The method may include: reducing a thickness of the semiconductor wafer; before or after reducing the thickness of the semiconductor wafer, placing a carrier structure at a first side of the semiconductor wafer; and after reducing the thickness of the semiconductor wafer, providing a support structure at a second side of the semiconductor wafer opposite to the first side. Methods for welding a support structure onto a semiconductor wafer are proposed. Further, semiconductor composite structures with support structures welded onto a semiconductor wafer are proposed.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 10, 2022
    Inventors: Francisco Javier Santos Rodriguez, Alexander Breymesser, Erich Griebl, Michael Knabl, Matthias Kuenle, Andreas Moser, Roland Rupp, Hans-Joachim Schulze, Sokratis Sgouridis, Stephan Voss
  • Publication number: 20220359194
    Abstract: A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 10, 2022
    Inventors: Iris MODER, Bernhard GOLLER, Tobias Franz Wolfgang HOECHBAUER, Roland RUPP, Francisco Javier SANTOS RODRIGUEZ, Hans-Joachim SCHULZE
  • Patent number: 11476111
    Abstract: A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: October 18, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Iris Moder, Bernhard Goller, Tobias Franz Wolfgang Hoechbauer, Roland Rupp, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
  • Publication number: 20220293558
    Abstract: A method for forming semiconductor devices includes: attaching a glass structure to a wide band-gap semiconductor wafer having a plurality of semiconductor devices; forming at least one pad structure electrically connected to at least one doping region of a semiconductor substrate of the wide band-gap semiconductor wafer, by forming electrically conductive material within at least one opening extending through the glass structure; and reducing a thickness of the wide band-gap semiconductor wafer after attaching the glass structure. Additional methods for forming semiconductor devices are described.
    Type: Application
    Filed: June 1, 2022
    Publication date: September 15, 2022
    Inventors: Roland Rupp, Alexander Breymesser, Andre Brockmeier, Carsten von Koblinski, Francisco Javier Santos Rodriguez, Ronny Kern