Abstract: A phase-locked loop comprises a voltage controlled oscillator. The voltage controlled oscillator comprises an inductor and a capacitor, connected in parallel, and also connected in parallel therewith, a negative resistance structure. A first terminal of the negative resistance structure is connected to respective first terminals of the inductor and the capacitor. A second terminal of the negative resistance structure is connected to respective second terminals of the inductor and the capacitor. The negative resistance structure exhibits a tunable capacitance, such that a frequency of an output of the voltage controlled oscillator can be tuned by a control input signal, and the control input signal is generated in the phase-locked loop. The negative resistance structure comprises first and second transistors.

Abstract: A phase-locked loop comprises a voltage controlled oscillator. The voltage controlled oscillator comprises an inductor and a capacitor, connected in parallel, and also connected in parallel therewith, a negative resistance structure. A first terminal of the negative resistance structure is connected to respective first terminals of the inductor and the capacitor. A second terminal of the negative resistance structure is connected to respective second terminals of the inductor and the capacitor. The negative resistance structure exhibits a tunable capacitance, such that a frequency of an output of the voltage controlled oscillator can be tuned by a control input signal, and the control input signal is generated in the phase-locked loop. The negative resistance structure comprises first and second transistors.

Abstract: A TI-ADC (50) comprising a group of sub-ADCs (A1-AM+N) is disclosed. During operation, M?2 of the sub-ADCs (A1-AM+N) are simultaneously operated for converting M respective consecutive input signal samples of the TI-ADC (50) from an analog to a digital representation. The total number of sub-ADCs (A1-AM+N) in the group is M+N, N?1. The TI-ADC (50) comprises error-estimation circuitry (60) for estimating errors of the sub-ADCs (A1-AM+N). Furthermore, the TI-ADC (50) comprises a control circuit (55) configured to, for each input signal sample, assign which sub-ADC (A1-AM+N) is to operate on that input signal sample. The control circuit (55) is configured to, for sub-ADCs (Ak1) in a first subset of the group of sub-ADCs (A1-AM+N), which are subject to error estimation by the error-estimation circuitry (60), perform the assignment according to a first scheme.

Abstract: A TI-ADC (50) comprising a group of sub-ADCs (A1-AM+N) is disclosed. During operation, M?2 of the sub-ADCs (A1-AM+N) are simultaneously operated for converting M respective consecutive input signal samples of the TI-ADC (50) from an analog to a digital representation. The total number of sub-ADCs (A1-AM+N) in the group is M+N, N?1. The TI-ADC (50) comprises error-estimation circuitry (60) for estimating errors of the sub-ADCs (A1-AM+N). Furthermore, the TI-ADC (50) comprises a control circuit (55) configured to, for each input signal sample, assign which sub-ADC (A1-AM+N) is to operate on that input signal sample. The control circuit (55) is configured to, for sub-ADCs (Ak1) in a first subset of the group of sub-ADCs (A1-AM+N), which are subject to error estimation by the error-estimation circuitry (60), perform the assignment according to a first scheme.

Abstract: A pipelined ADC includes a first sub ADC and a second sub ADC. The second sub ADC is configured to receive, as an input, an analog residue generated by the first sub ADC. The first sub ADC is configured to operate in a first conversion phase, generating a digital output of the first sub ADC, and a second conversion phase, generating the analog residue. The first sub ADC includes a reference-voltage generator circuit configured to generate a reference voltage of the first sub ADC and having a first mode of operation and a second mode of operation, in which the noise power of the reference voltage is less than in the first mode of operation. The reference-voltage generator circuit is configured to operate in its first mode of operation in the first conversion phase and in its second mode of operation in the second conversion phase.

Abstract: A pipelined ADC (25) is disclosed, comprising a first sub ADC (50) and a second sub ADC (60). The second sub ADC (60) is configured to receive, as an input, an analog residue generated by the first sub ADC (50). The first sub ADC (50) is configured to operate in a first conversion phase, in which it generates a digital output of the first sub ADC (50), and a second conversion phase, in which it generates the analog residue. The first sub ADC (50) comprises a reference-voltage generator circuit (52) configured to generate a reference voltage (vref) of the first sub ADC (50) and having a first mode of operation and a second mode of operation, in which the noise power of the reference voltage (vref) is less than in the first mode of operation. The reference-voltage generator circuit (52) is configured to operate in its first mode of operation in the first conversion phase and in its second mode of operation in the second conversion phase.

Abstract: A radio frequency receiver having a plurality of parallel receiving paths, wherein each path can receive a radio frequency signal in one of a plurality of radio frequency bands and amplify the received signal in a low noise amplifier. The amplified signals from the plurality of parallel paths are combined to one combined radio frequency signal in a common summation node and down-converted to a lower frequency signal in a mixer circuit. Each low noise amplifier comprises a low noise transconductance circuit providing a current signal to drive the common summation node, and an automatic gain control circuit in each path compensates for variations in signal strength independently of signal strengths of signals received by the other receiving paths. The receiver is suitable for simultaneous multiple band reception, where received signal strength can vary between the frequency bands.

Abstract: A radio frequency receiver having a plurality of parallel receiving paths, wherein each path can receive a radio frequency signal in one of a plurality of radio frequency bands and amplify the received signal in a low noise amplifier. The amplified signals from the plurality of parallel paths are combined to one combined radio frequency signal in a common summation node and down-converted to a lower frequency signal in a mixer circuit. Each low noise amplifier comprises a low noise transconductance circuit providing a current signal to drive the common summation node, and an automatic gain control circuit in each path compensates for variations in signal strength independently of signal strengths of signals received by the other receiving paths. The receiver is suitable for simultaneous multiple band reception, where received signal strength can vary between the frequency bands.

Abstract: A radio frequency receiver comprises a plurality of parallel receiving paths, wherein each path can receive a radio frequency signal in one of a plurality of radio frequency bands and amplify the received signal in a low noise amplifier. The amplified signals from the plurality of parallel paths are combined to one combined radio frequency signal in a common summation node and down-converted to a lower frequency signal in a mixer circuit. Each low noise amplifier comprises a low noise transconductance circuit providing a current signal to drive the common summation node, and an automatic gain control circuit in each path compensates for variations in signal strength independently of signal strengths of signals received by the other receiving paths. The receiver is suitable for simultaneous multiple band reception, where received signal strength can vary between the frequency bands.

Abstract: A radio frequency receiver comprises a plurality of parallel receiving paths, wherein each path can receive a radio frequency signal in one of a plurality of radio frequency bands and amplify the received signal in a low noise amplifier. The amplified signals from the plurality of parallel paths are combined to one combined radio frequency signal in a common summation node and down-converted to a lower frequency signal in a mixer circuit. Each low noise amplifier comprises a low noise transconductance circuit providing a current signal to drive the common summation node, and an automatic gain control circuit in each path compensates for variations in signal strength independently of signal strengths of signals received by the other receiving paths. The receiver is suitable for simultaneous multiple band reception, where received signal strength can vary between the frequency bands.

Abstract: In a time-interleaved Analog to Digital Converter, circuit components and capacitances may be shared among a plurality of sample and hold circuits in each of two sets. The two shared circuits alternate, on different half-periods of a master clock signal, between charging a capacitance and sampling an input in an overlapping manner such that one is charging while the other is sampling. One sample and hold circuit is activated during each successive half-period (following a charging half-period) by independent, sequential, non-overlapping clocking signals. To improve SNDR, at least one switch is bootstrapped by driving its gate terminal with the voltage of a capacitor configured between the gate and the input signal. By sharing at least some components among multiple sample and hold circuits, the number of gates driven by clock signals is reduced, reducing clock distribution and calibration complexity, and the circuit area is reduced.

Abstract: An attenuator control method of a signal processing chain comprising two or more signal processing units is disclosed. One of the two or more signal processing units is a signal attenuator adapted to apply adaptive signal attenuation of an attenuator input signal based on one or more attenuation parameters to provide an attenuator output signal. At least one of the two or more signal processing units has an associated wearout process and a corresponding wearout budget, wherein a wearout event of the wearout process occurs when a level of a wearout indication signal of the signal processing chain is in a wearout region, and wherein the wearout process is modeled by a wearout event cost associated with a corresponding wearout event. The method comprises obtaining an indication of whether a wearout event of the wearout process has occurred.

Abstract: A technique for calibrating a receiver apparatus comprising at least one analog signal processing component and an intermediate frequency, or IF, mixer for converting IF signals comprising an in-phase, or I, signal and a quadrature-phase, or Q, signal to baseband frequency signals is provided. The IF mixer is arranged downstream of the at least one analog signal processing component. A method implementation of the technique comprises the steps of determining, in a digital processing domain downstream of the IF mixer, a metric which is affected by a frequency dependency of an imbalance between I and the Q signal, or IQ-imbalance, over a signal bandwidth, generating, based on the metric thus determined, a calibration signal configured to at least partially compensate a frequency-dependency of the IQ imbalance, and feeding the calibration signal to the at least one analog signal processing component so as to calibrate the at least one analog signal processing component.

Abstract: A technique for calibrating a receiver apparatus comprising at least one analog signal processing component and an intermediate frequency, or IF, mixer for converting IF signals comprising an in-phase, or I, signal and a quadrature-phase, or Q, signal to baseband frequency signals is provided. The IF mixer is arranged downstream of the at least one analog signal processing component. A method implementation of the technique comprises the steps of determining, in a digital processing domain downstream of the IF mixer, a metric which is affected by a frequency dependency of an imbalance between I and the Q signal, or IQ-imbalance, over a signal bandwidth, generating, based on the metric thus determined, a calibration signal configured to at least partially compensate a frequency-dependency of the IQ imbalance, and feeding the calibration signal to the at least one analog signal processing component so as to calibrate the at least one analog signal processing component.

Abstract: A conversion circuit for converting a complex analog input signal having an in-phase (I) component and a quadrature-phase (Q) component is disclosed. It comprises a channel-selection filter configured to filter the complex analog input signal, thereby generating a channel-filtered I and Q components, and one or more processing circuits. Each processing circuit comprises four mixers for generating a first and a second frequency-translated I component, and a first and a second channel-filtered Q component based on two LO signals with equal LO frequency and a 90° mutual phase shift. Each processing circuit also comprises a combiner circuit for generating a first, a second, a third, and a fourth combined signal proportional to sums and differences between the frequency translated I and Q components. The first and the fourth combined signals form a first complex signal, and the second and the third combined signals form a second complex signal.

Abstract: A conversion circuit (20) for converting a complex analog input signal having an in-phase, I, component and a quadrature-phase, Q, component resulting from frequency down conversion of a radio-frequency, RF, signal (XRF) to a frequency band covering 0 Hz into a digital representation is disclosed. It comprises a channel-selection filter unit (40) arranged to filter the complex analog input signal, thereby generating a channel-filtered I and Q components, and one or more processing units (53, 53a-b). Each processing unit comprises four mixers (60-75) for generating a first and a second frequency-translated I component and a first and a second channel-filtered Q component based on two LO signals with equal LO frequency and a 90° mutual phase shift. Furthermore, each processing unit comprises a combiner unit (85, 120) for generating a first, a second, a third, and a fourth combined signal proportional to sums and differences between said frequency translated I and Q components.

Abstract: A mixer arrangement for generating an analog output signal by mixing an analog input signal with a discrete-time mixing signal. The mixer arrangement comprises a plurality of unit elements. Each unit element is adapted to be in an enabled mode in a first state of an enable signal supplied to the unit element, and in a disabled mode in a second state of the enable signal. Each unit element is adapted to generate the output signal of the unit element based on the analog input signal of the mixer arrangement in the enabled mode but not in the disabled mode. The unit elements are connected for generating a common output signal as the sum of the output signals from the unit elements. The mixer arrangement is adapted to generate the analog output signal of the mixer arrangement based on the common output signal. A corresponding method is also disclosed.

Abstract: Efficient carrier aggregation is enabled in a receiver employing a single frequency source, and dividing the frequency source by different frequency dividing factors to generate two or more RF LO frequencies. Received signals are down-converted to intermediate frequencies by mixing with the respective RF LO frequencies. By utilizing only a single high frequency source, embodiments of the present invention avoid spurious and injection locking issues that arise when integrating two or more frequency sources, and additionally reduce power consumption as compared to a multiple frequency source solution.

Abstract: A conversion circuit (20) for converting a complex analog input signal having an in-phase, I, component and a quadrature-phase, Q, component resulting from frequency down conversion of a radio-frequency, RF, signal (XRF) to a frequency band covering 0 Hz into a digital representation is disclosed. It comprises a channel-selection filter unit (40) arranged to filter the complex analog input signal, thereby generating a channel-filtered I and Q components, and one or more processing units (53, 53a-b). Each processing unit comprises four mixers (60-75) for generating a first and a second frequency-translated I component and a first and a second channel-filtered Q component based on two LO signals with equal LO frequency and a 90° mutual phase shift. Furthermore, each processing unit comprises a combiner unit (85, 120) for generating a first, a second, a third, and a fourth combined signal proportional to sums and differences between said frequency translated I and Q components.

Abstract: A mixer arrangement for generating an analog output signal mixing an analog input signal with a discrete-time mixing signal. The mixer arrangement comprises a plurality of unit elements. Each unit element is adapted to be in an enabled mode in a first state of an enable signal supplied to the unit element, and in a disabled mode in a second state of the enable signal. Each unit element is adapted to generate the output signal of the unit element based on the analog input signal of the mixer arrangement in the enabled mode but not in the disabled mode. The unit elements are connected for generating a common output signal as the sum of the output signals from the unit elements. The arrangement is adapted to generate the analog output signal of the mixer arrangement based on the common output signal. A corresponding method is also disclosed.