Abstract: Efficient carrier aggregation is enabled in a receiver employing a single frequency source, and dividing the frequency source by different frequency dividing factors to generate two or more RF LO frequencies. Received signals are down-converted to intermediate frequencies by mixing with the respective RF LO frequencies. By utilizing only a single high frequency source, embodiments of the present invention avoid spurious and injection locking issues that arise when integrating two or more frequency sources, and additionally reduce power consumption as compared to a multiple frequency source solution.

Abstract: The control word input to a Digitally Controlled Oscillator (DCO) is modified to reduce non-monotonic regions in the output response of the DCO. The DCO may be included in a Phase-Locked Loop (PLL) circuit for generating an output signal that locks onto either the phase or frequency of a reference signal input. By modifying the control word input to the DCO to avoid non-monotonic regions in the DCO output response, PLL phase noise is reduced. In one embodiment, the control word is modified by reordering or skipping control word values input to the DCO that correspond to non-monotonic regions in the output response of the DCO circuit.

Abstract: A time delay line comprises a plurality of delay elements connected in series. Each delay element comprises one or more transistors that exhibit a reverse short channel effect at channel lengths within a certain range. The transistors are configured to have a channel length in the certain range in order to reduce time delay sensitivity to process variations.

Abstract: The control word input to a Digitally Controlled Oscillator (DCO) is modified to reduce non-monotonic regions in the output response of the DCO. The DCO may be included in a Phase-Locked Loop (PLL) circuit for generating an output signal that locks onto either the phase or frequency of a reference signal input. By modifying the control word input to the DCO to avoid non-monotonic regions in the DCO output response, PLL phase noise is reduced. In one embodiment, the control word is modified by reordering or skipping control word values input to the DCO that correspond to non-monotonic regions in the output response of the DCO circuit.

Abstract: A controlled oscillator generates an output signal having a frequency that is controllable by an input signal. The oscillator includes a switchable variable capacitor arrangement for tuning an output frequency of the controlled oscillator; and circuitry that, in combination with the switchable variable capacitor arrangement, generates an oscillating signal whose frequency is, at least in part, a function of a total capacitance of the switchable variable capacitor arrangement. The switchable variable capacitor arrangement includes a plurality of variable capacitors, each tunable by means of a tuning control signal and a switch arrangement that selectively opens or closes electrical paths to one or more of the variable capacitors under the control of one or more switch control signals, wherein the number of variable capacitors that contribute to the total capacitance of the switchable variable capacitor arrangement is controlled by states of the one or more switch control signals.