Abstract: A number of different sealed interfaces for power modules are described. In one example, a sealed interface includes a printed circuit board including a contact pad for power conduction to a bus bar of the printed circuit board, a semiconductor module including at least one power transistor, a terminal pin electrically coupled to the power module, and a housing for the power module. The housing includes an open terminal aperture that extends through the housing. The printed circuit board is seated upon the open terminal aperture, to close and seal the open terminal aperture, with the contact pad positioned within the open terminal aperture. The terminal pin contacts the contact pad of the printed circuit board within the open terminal aperture, and the open terminal aperture comprises a transitional feature to abate electric field intensity around an interface between the open terminal aperture and the printed circuit board.

Abstract: A multi-three-phase motor drive system includes a power distribution network, a motor drive unit, and a motor network. The power distribution network includes a partitioned direct current (DC) link connected between a positive voltage rail and a negative voltage rail. A connection between the positive voltage rail and a mid-point node defines an upper portion of the partitioned DC link and a connection between negative voltage rail and the mid-point node defines a lower portion of the partitioned DC link. The motor drive unit includes a plurality of inverter units, and the motor network includes a plurality of motor windings which are each connected to a respective inverter unit. A first group of the inverter units is connected in parallel with the upper portion of the portioned DC link, and a second group of the inverter units is connected in parallel with the lower portion of the partitioned DC link.

Abstract: Power systems including converters that exhibit reduced common mode voltage emissions are described. In one example, a power converter system includes an input and an output, a multi-level switch bridge coupled between the input and the output, an input capacitor branch coupled across the input, an output capacitor branch coupled across the output, and a controller configured to generate switching control signals for the multi-level buck-boost switch bridge. The multi-level switch bridge also includes a plurality of inductors in one example. In one case, a quadrangular or quadrangle control mode can be relied upon to switch the multi-level switch bridge, to minimize the ripple in the inductors, achieve zero voltage switching, reduce common mode electromagnetic interference emission by the converter, and for other benefits.

Abstract: Aspects of switching-cycle voltage deviation control for modular multilevel converters (MMCs) are described. In one example, an upper switching action of an upper power cell is determined within a time duration of a switching cycle for an MMC. In addition, a lower switching action of a lower power cell is determined within the time duration of the switching cycle for the MMC. In addition, a delay is generated between the upper switching action and the lower switching action to reduce capacitor voltage deviation between the upper power cell and the lower power cell during the switching cycle. The upper power cell is located in an upper arm of a phase leg of the MMC, while the lower power cell is located in a lower arm of the phase leg of the MMC.

Abstract: Topologies and configurations of step-down power supplies including unidirectional balancing cells are described. In one example, a step-down power supply includes an input and an output, a string of series-connected capacitors, and a plurality of unidirectional balancing cells coupled to the capacitors in the string of series-connected capacitors. A first balancing can be configured to transfer power, unilaterally, in a first direction among at least two capacitors in the string of series-connected capacitors, and a second balancing cell can be configured to transfer power, unilaterally, in a second direction among at least two capacitors in the string of series-connected capacitors, where the first direction is different than the second direction. The power supply can also include a gate controller for a balancing cell. The gate controller generates switching control signals at a first switching frequency that is decoupled from a resonant frequency of a balancing branch in the balancing cell.

Abstract: Various examples of power converters including Integrated Capacitor Blocked Transistor (ICBT) cells and methods of control of power converters having ICBT cells are described. In one example, a power converter includes an upper arm including a plurality of upper ICBT cells connected in series to form a series connection path and a lower arm including a plurality of lower ICBT cells connected in series in the series connection path. A controller can be configured to provide a control signal pair to each of the upper ICBT cells and a complementary control signal pair to each of the lower ICBT cells to control the converter output. A capacitor voltage controller can be configured to balance a voltage potential among ICBT capacitors in at least one of the upper arm and the lower arm.

Abstract: A switching bridge for the DC-DC stage of a power converter, the switching bridge having one or more sets of upper and lower series-connected switches (S1, S2) connected across a DC bus and arranged to be switched to provide an output AC voltage, the switching bridge further comprising a voltage divider (C1) arranged to vary the output AC voltage level according to the switching state of the switches.

Abstract: Aspects are described for hybrid modular multilevel converters that include half-bridge submodules. In some embodiments, a hybrid modular multilevel converter can include a direct current (DC) bus and an alternating current (AC) node. A first arm of the hybrid modular multilevel converter includes a first submodule chain link and a first arm inductor and a second arm includes a second submodule chain link and a second arm inductor. A capacitor connects between a first side of the first arm and a first side of the second arm.

Abstract: A number of different sealed interfaces for power modules are described. In one example, a sealed interface includes a printed circuit board including a contact pad for power conduction to a bus bar of the printed circuit board, a semiconductor module including at least one power transistor, a terminal pin electrically coupled to the power module, and a housing for the power module. The housing includes an open terminal aperture that extends through the housing. The printed circuit board is seated upon the open terminal aperture, to close and seal the open terminal aperture, with the contact pad positioned within the open terminal aperture. The terminal pin contacts the contact pad of the printed circuit board within the open terminal aperture, and the open terminal aperture comprises a transitional feature to abate electric field intensity around an interface between the open terminal aperture and the printed circuit board.

Abstract: Gate control of power semiconductor devices using reduced gate drivers is disclosed. A circuit breaker may include a multitude of transistors, such as insulated gate bipolar transistors (IGBTs), connected in series with one another. Each transistor may be connected to a respective gate resistor. Diodes may be connected between various gate resistors. One or more resistor-capacitor (RC) snubber circuits may be provided in parallel with one or more of the transistors. Likewise, one or more metal-oxide varistors (MOVs) may be connected in parallel to one or more of the transistors. A gate driver (e.g., a single gate drive) may be connected to the one or more diodes and an emitter of at least one of transistors.

Abstract: Aspects are described for hybrid modular multilevel converters that include half-bridge submodules. In some embodiments, a hybrid modular multilevel converter can include a direct current (DC) bus and an alternating current (AC) node. A first arm of the hybrid modular multilevel converter includes a first submodule chain link and a first arm inductor and a second arm includes a second submodule chain link and a second arm inductor. A capacitor connects between a first side of the first arm and a first side of the second arm.

Abstract: A voltage balancing circuit for use in a power converter is described. In one example, a power converter includes series-connected switching transistors for power conversion, and a voltage balancing control loop. The voltage balancing control loop includes a measurement circuit electrically coupled to a transistor in the pair of series-connected switching transistors. The measurement circuit is electrically coupled to measure a body voltage reference of the transistor. The voltage balancing control loop also includes a balancing circuit configured to generate a balancing pulse signal for adjusting a voltage across the transistor using the body voltage reference, and a circuit configured to combine the balancing pulse signal with a gate drive pulse signal for the transistor, to form a balanced gate drive pulse signal for the transistor. The balanced gate drive pulse signal helps to equalize the body diode voltages of the series-connected switching transistors, particularly during “off” periods.

Abstract: Aspects of hybrid-current-mode switching-cycle control are described. In one embodiment, a peak current mode is selected to control a switching power cell. The switching power cell is in an arm of a phase leg of a modular multilevel converter. The phase leg includes an upper arm and a lower arm, and the switching power cell includes a capacitor and at least one switch. At least one switch control signal switches the switching power cell according to a peak current mode based on at least one arm current boundary crossing identified for the arm.

Abstract: Various embodiments of laminated planar bus structures that minimize electromagnetic interference (EMI) and parasitic inductance are described. In one embodiment, a laminated planar bus structure may include a plurality of stacked conductive layers and a plurality of stacked insulation layers. The plurality of stacked conductive layers may include positive and negative conductive layers, and conductive ground layers stacked as outer layers as to enclose vertically the positive and the negative conductive layers. In another embodiment, the laminated planar bus structure may include a middle ground layer stacked in between the positive and the negative conductive layers to provide additional reduction in electric field strength. A laminated planar bus structure that is integrated with other power electronics components is also presented.

Abstract: Various examples of a high frequency, inductor and transformer core loss characterization and measurement method and system for arbitrary waveforms are disclosed herein. A system and method for determining core loss of a magnetic core can include generating a waveform to excite a first test circuit which comprises an excitation circuit, a circuit under test (CUT) comprising the magnetic core, and an inductance circuit having an inductor connected in parallel to the CUT. The method includes measuring a first current, when the first test circuit is excited. The method includes disconnecting the CUT from the first test circuit to form a second test circuit. The method includes generating the waveform to excite the second test circuit, and measuring a second current, when the second test circuit is excited. The power loss for the magnetic core is calculated based on an input voltage and the first and second measured current.

Abstract: A voltage balancing circuit for use in a power converter is described. In one example, a power converter includes series-connected switching transistors for power conversion, and a voltage balancing control loop. The voltage balancing control loop includes a measurement circuit electrically coupled to a transistor in the pair of series-connected switching transistors. The measurement circuit is electrically coupled to measure a body voltage reference of the transistor. The voltage balancing control loop also includes a balancing circuit configured to generate a balancing pulse signal for adjusting a voltage across the transistor using the body voltage reference, and a circuit configured to combine the balancing pulse signal with a gate drive pulse signal for the transistor, to form a balanced gate drive pulse signal for the transistor. The balanced gate drive pulse signal helps to equalize the body diode voltages of the series-connected switching transistors, particularly during “off” periods.

Abstract: Aspects of bidirectional architectures with partial energy processing in resonant direct current (DC)-to-DC converters are described. In one embodiment, an alternating circuit (AC)-to-DC circuit generates an AC voltage from a DC voltage. A voltage of the AC voltage is transformed into a majority AC voltage of a majority power path and at least one minority AC voltage of the minority power paths. The majority AC voltage is rectified into a majority DC voltage and a minority AC voltage is rectified into a minority DC voltage. The majority power path and the minority power path are combined as a combined DC voltage.

Abstract: An inverter with a modular bus assembly is described. In various embodiments, the modular bus assembly includes a laminated motherboard and a plurality of capacitor daughtercards. The laminated motherboard can be configured to interface a plurality of phase-leg modules and a plurality of capacitor daughtercards through a plurality of terminals and connectors located on a bottom side or a top side of the laminated motherboard. The laminated motherboard includes a layer stack with a plurality of conductor layers. Each of the plurality of conductor layers is implemented with a net spacing from a neighboring plated through hole (PTH) based at least in part on differences in potential to be applied to each of the plurality of conductor layers as compared to a potential to be applied to the PTH. Embedded shield polygons can be implemented on the laminated motherboard to mitigate surface discharge at surface terminal (PTH/SMT) triple junctions.

Abstract: Various examples of a high frequency, inductor and transformer core loss characterization and measurement method and system for arbitrary waveforms are disclosed herein. A system and method for determining core loss of a magnetic core can include generating a waveform to excite a first test circuit which comprises an excitation circuit, a circuit under test (CUT) comprising the magnetic core, and an inductance circuit having an inductor connected in parallel to the CUT. The method includes measuring a first current, when the first test circuit is excited. The method includes disconnecting the CUT from the first test circuit to form a second test circuit. The method includes generating the waveform to excite the second test circuit, and measuring a second current, when the second test circuit is excited. The power loss for the magnetic core is calculated based on an input voltage and the first and second measured current.

Abstract: Aspects of bidirectional architectures with partial energy processing in resonant direct current (DC)-to-DC converters are described. In one embodiment, an alternating circuit (AC)-to-DC circuit generates an AC voltage from a DC voltage. A voltage of the AC voltage is transformed into a majority AC voltage of a majority power path and at least one minority AC voltage of the minority power paths. The majority AC voltage is rectified into a majority DC voltage and a minority AC voltage is rectified into a minority DC voltage. The majority power path and the minority power path are combined as a combined DC voltage.