Abstract: A true complement dynamic circuit for combining, in particular comparing, binary data on dynamic first and second input signals to third and fourth input signals, comprising at least a 1-bit compare circuit, wherein the dynamic first and second input signals are complementary signals during an evaluation phase, wherein a logical behavior is determined by the third and fourth input signals. A method for operating a true complement dynamic circuit for combining, in particular comparing, binary data on dynamic first and second input signals to third and fourth input signals, comprising operating at least a 1-bit compare circuit, wherein the dynamic first and second input signals are complementary signals during an evaluation phase, determining a logical behavior by the third and fourth input signals.

Abstract: A true complement dynamic circuit for combining, in particular comparing, binary data on dynamic first and second input signals to third and fourth input signals, comprising at least a 1-bit compare circuit, wherein the dynamic first and second input signals are complementary signals during an evaluation phase, wherein a logical behavior is determined by the third and fourth input signals. A method for operating a true complement dynamic circuit for combining, in particular comparing, binary data on dynamic first and second input signals to third and fourth input signals, comprising operating at least a 1-bit compare circuit, wherein the dynamic first and second input signals are complementary signals during an evaluation phase, determining a logical behavior by the third and fourth input signals.

Abstract: An integrated circuit includes at least one first area including logic circuitry. The logic circuitry includes library blocks selected from a logic circuit library. A first one of the library blocks is provided with at least two symmetry mirror edges perpendicular to a height of the library blocks. Two adjacent ones of the library blocks are joined at a common symmetry mirror edge.

Abstract: An embodiment may include an integrated circuit. The integrated circuit may include a plurality of vertical transistor structures arranged in a two-dimensional grid pattern including a longitudinal set of grid-lines, a transversal set of grid-lines, and nodes at each intersection of the longitudinal set of grid-lines and the transversal set of grid-lines. Each vertical transistor structure is arranged substantially perpendicular to the plurality of layers of the integrated circuit and aligned with each node of the two-dimensional grid pattern.

Abstract: An embodiment may include a method of forming a microelectronic device. The method may include forming a pair of transistors stacked vertically and connected in series, each of the pair of transistors are of the same type. The method may include forming a memory element including a first inverter containing a first inverter transistor and an access transistor. The first inverter transistor is connected to a power supply rail. The access transistor is connected to a bitline. The first inverter transistor is a first transistor of the pair of vertically stacked transistors and the access transistor is a second transistor of the pair of vertically stacked transistors. The pair of transistors are arranged substantially perpendicular to the plurality of layers.

Abstract: An integrated circuit includes at least one first area including logic circuitry. The logic circuitry includes library blocks selected from a logic circuit library. A first one of the library blocks is provided with at least two symmetry mirror edges perpendicular to a height of the library blocks. Two adjacent ones of the library blocks are joined at a common symmetry mirror edge.

Abstract: Techniques for generating a layout of a multi-port memory cell are provided. A specification describing at least on port within a memory cell is defined. A base memory cell including at least one extension point is modeled. A port that interfaces with the base memory cell is identified from the specification. An electrical interface between the identified port and an extension point of the base memory cell is modeled. In some embodiments, a design bucket is selected from among a predefined set of design buckets based on a count of ports within the memory cell, as described by the specification. Each design bucket corresponding to a respective layout template including the base memory cell and a respective maximum count of ports. Each electrical interface including a port described in the specification of the memory cell is modeled based on the selected design bucket and the respective layout template.

Abstract: An embodiment may include a method of forming an integrated circuit. The method may include forming a first pair of transistors stacked vertically above a semiconductor substrate arranged substantially perpendicular to the plurality of layers. Each of the first pair of vertically stacked transistors are of the same type and are connected in series. The method may include forming a second pair of transistors connected in parallel and arranged substantially perpendicular to the plurality of layers. The second pair of transistors are a different type than the first pair of vertically stacked transistors. The method may include forming a power supply rail within the semiconductor substrate and arranged at one end of the first pair of vertically stacked transistors.

Abstract: An embodiment may include a microelectronic device. The microelectronic device may include a first pair of transistors stacked vertically and connected in series. Each of the first pair of transistors are of the same type. The microelectronic device may include a second pair of transistors connected in parallel. The second pair of transistors being a different type than the first pair of transistors. The first pair of transistors and the second pair of transistors are arranged substantially perpendicular to the plurality of layers.

Abstract: Techniques for generating a layout of a multi-port memory cell are provided. A specification describing at least on port within a memory cell is defined. A base memory cell including at least one extension point is modeled. A port that interfaces with the base memory cell is identified from the specification. An electrical interface between the identified port and an extension point of the base memory cell is modeled. In some embodiments, a design bucket is selected from among a predefined set of design buckets based on a count of ports within the memory cell, as described by the specification. Each design bucket corresponding to a respective layout template including the base memory cell and a respective maximum count of ports. Each electrical interface including a port described in the specification of the memory cell is modeled based on the selected design bucket and the respective layout template.

Abstract: An embodiment may include a method of forming a microelectronic device. The method may include forming a pair of transistors stacked vertically and connected in series, each of the pair of transistors are of the same type. The method may include forming a memory element including a first inverter containing a first inverter transistor and an access transistor. The first inverter transistor is connected to a power supply rail. The access transistor is connected to a bitline. The first inverter transistor is a first transistor of the pair of vertically stacked transistors and the access transistor is a second transistor of the pair of vertically stacked transistors. The pair of transistors are arranged substantially perpendicular to the plurality of layers.

Abstract: An embodiment may include a method of forming an integrated circuit. The method may include forming a first pair of transistors stacked vertically above a semiconductor substrate arranged substantially perpendicular to the plurality of layers. Each of the first pair of vertically stacked transistors are of the same type and are connected in series. The method may include forming a second pair of transistors connected in parallel and arranged substantially perpendicular to the plurality of layers. The second pair of transistors are a different type than the first pair of vertically stacked transistors. The method may include forming a power supply rail within the semiconductor substrate and arranged at one end of the first pair of vertically stacked transistors.

Abstract: An embodiment may include an integrated circuit. The integrated circuit may include a plurality of vertical transistor structures arranged in a two-dimensional grid pattern including a longitudinal set of grid-lines, a transversal set of grid-lines, and nodes at each intersection of the longitudinal set of grid-lines and the transversal set of grid-lines. Each vertical transistor structure is arranged substantially perpendicular to the plurality of layers of the integrated circuit and aligned with each node of the two-dimensional grid pattern.

Abstract: An embodiment may include a microelectronic device. The microelectronic device may include a first pair of transistors stacked vertically and connected in series. Each of the first pair of transistors are of the same type. The microelectronic device may include a second pair of transistors connected in parallel. The second pair of transistors being a different type than the first pair of transistors. The first pair of transistors and the second pair of transistors are arranged substantially perpendicular to the plurality of layers.

Abstract: The present invention provides a system and method of testing CAMs and RAMs. In an exemplary embodiment, the system includes a multiple input signature register (MISR) logically coupled to digital outputs of a CAM, to digital inputs of a RAM, and to digital outputs of an ABIST controller circuit, where the MISR includes a plurality of L1 latch circuits logically coupled to a plurality of L2 latch circuits, a plurality of multiplexer circuits logically coupled to the plurality of L1 latch circuits, a plurality of exclusive or circuits (inner XOR circuits) logically coupled to the plurality of MUX circuits and to the plurality of L2 latch circuits, and at least two XOR circuits (outer XOR circuits), each of the outer XOR circuits logically coupled to one of the inner XOR circuits, to at least one of the MUX circuits, and to at least one of the L2 latch circuits.

Abstract: A content addressable memory (CAM) cell system is provided. The CAM cell system includes a first memory cell, a first logic circuitry and a first compare circuitry. The first logic circuit includes a first n-FET, a first p-FET, and a first input terminal. A gate of the first n-FET and a gate of the first p-FET are galvanically coupled to the first input terminal. The first compare circuitry is communicatively coupled to the first memory cell via a first coupling, and to the first input terminal via a second coupling. The first compare circuitry is configured to receive first data stored in the first memory cell via the first coupling, receive first match data, transmit a first binary logical value to the first input terminal via the second coupling in response to the first data not matching the first match data, and transmit a second binary logical value to the first input terminal via the second coupling in response to the first data matching the first match data.

Abstract: The present invention provides a system and method of testing CAMs and RAMs. In an exemplary embodiment, the system includes a multiple input signature register (MISR) logically coupled to digital outputs of a CAM, to digital inputs of a RAM, and to digital outputs of an ABIST controller circuit, where the MISR includes a plurality of L1 latch circuits logically coupled to a plurality of L2 latch circuits, a plurality of multiplexer circuits logically coupled to the plurality of L1 latch circuits, a plurality of exclusive or circuits (inner XOR circuits) logically coupled to the plurality of MUX circuits and to the plurality of L2 latch circuits, and at least two XOR circuits (outer XOR circuits), each of the outer XOR circuits logically coupled to one of the inner XOR circuits, to at least one of the MUX circuits, and to at least one of the L2 latch circuits.

Abstract: The present invention provides a system and method of testing CAMs and RAMs. In an exemplary embodiment, the system includes a multiple input signature register (MISR) logically coupled to digital outputs of a CAM, to digital inputs of a RAM, and to digital outputs of an ABIST controller circuit, where the MISR includes a plurality of L1 latch circuits logically coupled to a plurality of L2 latch circuits, a plurality of multiplexer circuits logically coupled to the plurality of L1 latch circuits, a plurality of exclusive or circuits (inner XOR circuits) logically coupled to the plurality of MUX circuits and to the plurality of L2 latch circuits, and at least two XOR circuits (outer XOR circuits), each of the outer XOR circuits logically coupled to one of the inner XOR circuits, to at least one of the MUX circuits, and to at least one of the L2 latch circuits.

Abstract: The present invention provides a system and method of testing CAMs and RAMs. In an exemplary embodiment, the system includes a multiple input signature register (MISR) logically coupled to digital outputs of a CAM, to digital inputs of a RAM, and to digital outputs of an ABIST controller circuit, where the MISR includes a plurality of L1 latch circuits logically coupled to a plurality of L2 latch circuits, a plurality of multiplexer circuits logically coupled to the plurality of L1 latch circuits, a plurality of exclusive or circuits (inner XOR circuits) logically coupled to the plurality of MUX circuits and to the plurality of L2 latch circuits, and at least two XOR circuits (outer XOR circuits), each of the outer XOR circuits logically coupled to one of the inner XOR circuits, to at least one of the MUX circuits, and to at least one of the L2 latch circuits.

Abstract: A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line. The global bit-line is connected to a pre-charge circuit, and the pre-charge circuit is adapted for pre-charging the global bit-line with a programmable pre-charge voltage before reading data. The pre-charge circuit comprises a limiter circuit which comprises a pre-charge regulator circuit connected to the global bit-line to pre-charge the global bit-line with the programmable pre-charge voltage, and an evaluation and translation circuit connected to the pre-charge regulator circuit and the global bit-line to compensate leakage current of the global bit-line without changing its voltage level.