Patents by Inventor Romain Coffy

Romain Coffy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11437306
    Abstract: A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: September 6, 2022
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain Coffy, Fabien Quercia
  • Patent number: 11387381
    Abstract: An optoelectronic device includes an emitter of light rays and a receiver of light rays. The emitter is encapsulated in a transparent block. An opaque conductive layer is applied to a top surface and a side surface of the transparent block. The receiver is mounted to the opaque conductive layer at the top surface. An electrical connection is made between the receiver and the opaque conductive layer. A conductive strip is also mounted to the side surface of the transparent block and isolated from the opaque conductive layer. A further electrical connection is made between the receiver and the conductive strip.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: July 12, 2022
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain Coffy, Remi Brechignac, Jean-Michel Riviere
  • Patent number: 11380663
    Abstract: An opaque dielectric carrier and confinement substrate is formed by a stack of layers laminated on each other. The stack includes a solid back layer and a front frame having a peripheral wall and an intermediate partition which delimits two cavities located on top of the solid back layer and on either side of the intermediate partition. Electronic integrated circuit (IC) chips are located inside the cavities and mounted on top of the solid back layer. Each IC chip includes an integrated optical element. Electrical connections are provided between the IC chips and back electrical contacts of the solid back layer. Transparent encapsulation blocks are molded in the cavities to embed the IC chips.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: July 5, 2022
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain Coffy, Remi Brechignac, Jean-Michel Riviere
  • Publication number: 20220196938
    Abstract: An optoelectronic element is located in a package. The package includes a first optical block and a second optical block that are attached to each other by a bonding layer. One of the first and second optical blocks is attached to lateral walls of the package by glue. The material of the bonding layer is configured to induce less stress to the first and second optical blocks than the glue.
    Type: Application
    Filed: December 9, 2021
    Publication date: June 23, 2022
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain COFFY, Jean-Michel RIVIERE
  • Publication number: 20220187123
    Abstract: An electronic chip supports an optical device and electric connection zones. An insulating coating coats the electronic chip, covers the electric connection zones and exposes the optical device. An optical plugging element is at least partly fastened onto a first face of the insulating coating and is optically coupled to the optical device. Vias pass through the insulating coating from its first face to a second face opposite to the first face. Inner walls of the vias support electrically conductive paths connected to the electric connection zones of the electronic chip by electrically conductive tracks arranged on the first face of the insulating coating. The electrically conductive paths of the vias further have ends protruding onto the second face of the insulating coating.
    Type: Application
    Filed: December 8, 2021
    Publication date: June 16, 2022
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain COFFY, Younes BOUTALEB
  • Patent number: 11322666
    Abstract: An optoelectronic device includes an emitter of light rays and a receiver of light rays. The emitter is encapsulated within a first encapsulation layer, and the receiver is encapsulated within a second encapsulation layer. An opaque layer covers the first encapsulation layer (encapsulating the receiver) and covers the second encapsulation layer (encapsulating the emitter). The first and second encapsulation layers are separated by a region of opaque material. This opaque material may be provided by the opaque layer or an opaque fill.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: May 3, 2022
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain Coffy, Remi Brechignac, Jean-Michel Riviere
  • Patent number: 11211772
    Abstract: The disclosure concerns a housing for a light source mounted on a substrate, the housing comprising: a barrel comprising a mounting for a diffuser; and a diffuser positioned in the mounting, wherein the barrel comprises first and second conducting columns and a fuse or conductive wire electrically coupling the first and second conducting columns. A portion of the fuse is mechanically fixed to the diffuser and/or the fuse being arranged to trap the diffuser in said mounting.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: December 28, 2021
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Romain Coffy, Jean-Michel Riviere
  • Publication number: 20210398919
    Abstract: A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.
    Type: Application
    Filed: September 3, 2021
    Publication date: December 23, 2021
    Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Denis FARISON, Romain COFFY, Jean-Michel RIVIERE
  • Publication number: 20210366865
    Abstract: An integrated circuit chip includes a front face having an electrical connection pad. An overmolded encapsulation block encapsulates the integrated circuit chip and includes a front layer at least partially covering a front face of the integrated circuit chip. A through-hole the encapsulation block is located above the electrical connection pad of the integrated circuit chip. A wall of the through-hole is covered with an inner metal layer that is joined to the front pad of the integrated circuit chip. A front metal layer covers a local zone of the front face of the front layer, with the front metal layer being joined to the inner metal layer to form an electrical connection. The inner metal layer and the front metal layer are attached or anchored to activated additive particles that are included in the material of the encapsulation block.
    Type: Application
    Filed: August 6, 2021
    Publication date: November 25, 2021
    Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SAS
    Inventors: Romain COFFY, Patrick LAURENT, Laurent SCHWARTZ
  • Patent number: 11139255
    Abstract: A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: October 5, 2021
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Grenoble 2) SAS
    Inventors: Denis Farison, Romain Coffy, Jean-Michel Riviere
  • Patent number: 11114404
    Abstract: An integrated circuit chip includes a front face having an electrical connection pad. An overmolded encapsulation block encapsulates the integrated circuit chip and includes a front layer at least partially covering a front face of the integrated circuit chip. A through-hole the encapsulation block is located above the electrical connection pad of the integrated circuit chip. A wall of the through-hole is covered with an inner metal layer that is joined to the front pad of the integrated circuit chip. A front metal layer covers a local zone of the front face of the front layer, with the front metal layer being joined to the inner metal layer to form an electrical connection. The inner metal layer and the front metal layer are attached or anchored to activated additive particles that are included in the material of the encapsulation block.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: September 7, 2021
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SAS
    Inventors: Romain Coffy, Patrick Laurent, Laurent Schwartz
  • Publication number: 20210242115
    Abstract: A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.
    Type: Application
    Filed: February 2, 2021
    Publication date: August 5, 2021
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain COFFY, Fabien QUERCIA
  • Publication number: 20210202781
    Abstract: A device includes a substrate and an optoelectronic chip buried in the substrate. The substrate may include an opening above a first optical transduction region of the first optoelectronic chip and above a second optical transduction region of a second optoelectronic chip.
    Type: Application
    Filed: March 11, 2021
    Publication date: July 1, 2021
    Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Alexandre COULLOMB, Romain COFFY, Jean-Michel RIVIERE
  • Patent number: 11038595
    Abstract: An optoelectronic device includes a substrate and a first optoelectronic chip flush with a surface of the substrate. The device includes a cover that covers the substrate and the first optoelectronic chip. The cover comprises a cavity above a first optical transduction region of the first optoelectronic chip. The device also includes a second optoelectronic chip having a second optical transduction region spaced apart from the first optical transduction region and the cavity continues above the second optical transduction region.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: June 15, 2021
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Alexandre Coullomb, Romain Coffy, Jean-Michel Riviere
  • Publication number: 20210159985
    Abstract: A cover for an electronic circuit package, including: a body having an opening extending therethrough; a first element located in the opening and having a surface continuing planar or rounded shapes of a surface of the cover; and a second element of connection of the first element to the body.
    Type: Application
    Filed: February 5, 2021
    Publication date: May 27, 2021
    Inventors: Jean-Michel RIVIERE, Romain COFFY, Karine SAXOD
  • Publication number: 20210135069
    Abstract: An optoelectronic device includes an emitter of light rays and a receiver of light rays. The emitter is encapsulated within a first encapsulation layer, and the receiver is encapsulated within a second encapsulation layer. An opaque layer covers the first encapsulation layer (encapsulating the receiver) and covers the second encapsulation layer (encapsulating the emitter). The first and second encapsulation layers are separated by a region of opaque material. This opaque material may be provided by the opaque layer or an opaque fill.
    Type: Application
    Filed: October 15, 2020
    Publication date: May 6, 2021
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain COFFY, Remi BRECHIGNAC, Jean-Michel RIVIERE
  • Publication number: 20210135038
    Abstract: An optoelectronic device includes an emitter of light rays and a receiver of light rays. The emitter is encapsulated in a transparent block. An opaque conductive layer is applied to a top surface and a side surface of the transparent block. The receiver is mounted to the opaque conductive layer at the top surface. An electrical connection is made between the receiver and the opaque conductive layer. A conductive strip is also mounted to the side surface of the transparent block and isolated from the opaque conductive layer. A further electrical connection is made between the receiver and the conductive strip.
    Type: Application
    Filed: October 15, 2020
    Publication date: May 6, 2021
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain COFFY, Remi BRECHIGNAC, Jean-Michel RIVIERE
  • Patent number: 10996412
    Abstract: A carrier substrate includes a first network of electrical connections and recess. An electronic chip is mounted to the carrier substrate within the recess. The electronic chip includes an integrated guide of optical waves and a second network of electrical connections. A end section of an elongate optical cable is mounted on one side of the electronic chip with a longitudinal guide of optical waves optically coupled to the integrated guide of optical waves. Electrical connection elements are interposed between a face of the electronic chip and a bottom wall of the recess, such that first connect pads of the first electrical connection network are connected to second connect pads of the second electrical connection network through the electrical connection elements.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: May 4, 2021
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Florian Perminjat, Romain Coffy, Jean-Michel Riviere
  • Patent number: 10998470
    Abstract: A cover for an electronic circuit package, including an element having peripheral portions housed in an inner groove of a through opening.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 4, 2021
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Jean-Michel Riviere, Romain Coffy, Karine Saxod
  • Patent number: 10978607
    Abstract: A device includes a substrate and an optoelectronic chip buried in the substrate. The substrate may include an opening above a first optical transduction region of the first optoelectronic chip and above a second optical transduction region of a second optoelectronic chip.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: April 13, 2021
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Alexandre Coullomb, Romain Coffy, Jean-Michel Riviere