Patents by Inventor Roman Boschke
Roman Boschke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11114435Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to FinFET transistors. In one aspect, at least three fins are arranged to extend in parallel in a first direction and are laterally separated from each other in a second direction by shallow trench isolation structures having a first fin spacing, where at least a portion of each fin protrudes out from a substrate. At least a portion of each of a first fin and a second fin of the at least three fins vertically protrude to a level higher than an upper surface of the shallow trench isolation structures. A third fin is formed laterally between the first fin and the second fin in the second direction, where the third fin has a non-protruding region which extends vertically to a level below or equal to the upper surface of the shallow trench isolation structures.Type: GrantFiled: December 16, 2016Date of Patent: September 7, 2021Assignees: IMEC vzw, Katholieke Universiteit LeuvenInventors: Geert Hellings, Roman Boschke, Dimitri Linten, Naoto Horiguchi
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Publication number: 20170207217Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to FinFET transistors. In one aspect, at least three fins are arranged to extend in parallel in a first direction and are laterally separated from each other in a second direction by shallow trench isolation structures having a first fin spacing, where at least a portion of each fin protrudes out from a substrate. At least a portion of each of a first fin and a second fin of the at least three fins vertically protrude to a level higher than an upper surface of the shallow trench isolation structures. A third fin is formed laterally between the first fin and the second fin in the second direction, where the third fin has a non-protruding region which extends vertically to a level below or equal to the upper surface of the shallow trench isolation structures.Type: ApplicationFiled: December 16, 2016Publication date: July 20, 2017Inventors: Geert HELLINGS, Roman BOSCHKE, Dimitri LINTEN, Naoto HORIGUCHI
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Patent number: 9659928Abstract: By forming a trench isolation structure after providing a high-k dielectric layer stack, direct contact of oxygen-containing insulating material of a top surface of the trench isolation structure with the high-k dielectric material in shared polylines may be avoided. This technique is self-aligned, thereby enabling further device scaling without requiring very tight lithography tolerances. After forming the trench isolation structure, the desired electrical connection across the trench isolation structure may be re-established by providing a further conductive material.Type: GrantFiled: March 11, 2015Date of Patent: May 23, 2017Assignee: Advanced Micro Devices, Inc.Inventors: Andy Wei, Roman Boschke, Markus Forsberg
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Patent number: 9515155Abstract: E-fuses are used in integrated circuits in order to permit real-time dynamic reprogramming of the circuit after manufacturing. An e-fuse is hereby proposed wherein the metal element adapted to be blown upon passage of a current is not comprised of a silicide layer but is rather a metal layer above which a semiconductor layer is formed. A dielectric layer is then formed on the semiconductor layer, in order to prevent metal silicide from forming over the metal layer. The process of manufacturing the e-fuse can be easily integrated in an HKMG manufacturing flow. In particular, fully silicided metal gates may be manufactured in conjunction with the e-fuse, without jeopardizing the correct functioning of the e-fuse.Type: GrantFiled: December 20, 2013Date of Patent: December 6, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Roman Boschke, Stefan Flachowsky, Maciej Wiatr, Christian Schippel
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Patent number: 9450073Abstract: By reconfiguring material in a recess formed in drain and source regions of SOI transistors, the depth of the recess may be increased down to the buried insulating layer prior to forming respective metal silicide regions, thereby reducing series resistance and enhancing the stress transfer when the corresponding transistor element is covered by a highly stressed dielectric material. The material redistribution may be accomplished on the basis of a high temperature hydrogen bake.Type: GrantFiled: November 8, 2007Date of Patent: September 20, 2016Assignee: Advanced Micro Devices, Inc.Inventors: Andy Wei, Thorsten Kammler, Roman Boschke, Casey Scott
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Patent number: 9431508Abstract: When forming field effect transistors according to the gate-first HKMG approach, the cap layer formed on top of the gate electrode had to be removed before the silicidation step, resulting in formation of a metal silicide layer on the surface of the gate electrode and of the source and drain regions of the transistor. The present disclosure improves the manufacturing flow by skipping the gate cap removal process. Metal silicide is only formed on the source and drain regions. The gate electrode is then contacted by forming an aperture through the gate material, leaving the surface of the gate metal layer exposed.Type: GrantFiled: October 7, 2013Date of Patent: August 30, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Stefan Flachowsky, Jan Hoentschel, Roman Boschke
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Patent number: 9236440Abstract: When forming field effect transistors, a common problem is the formation of a Schottky barrier at the interface between a metal thin film in the gate electrode and a semiconductor material, typically polysilicon, formed thereupon. Fully silicided gates are known in the state of the art which may overcome this problem. The claimed method proposes an improved fully silicided gate achieved by forming a gate structure including an additional metal layer between the metal gate layer and the gate semiconductor material. A silicidation process can then be optimized so as to form a lower metal silicide layer comprising the metal of the additional metal layer and an upper metal silicide layer forming an interface with the lower metal silicide layer.Type: GrantFiled: December 5, 2013Date of Patent: January 12, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Roman Boschke, Stefan Flachowsky, Elke Erben
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Patent number: 9117929Abstract: By using an implantation mask having a high intrinsic stress, SMT sequences may be provided in which additional lithography steps may be avoided. Consequently, a strain source may be provided without significantly contributing to the overall process complexity.Type: GrantFiled: May 16, 2011Date of Patent: August 25, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Frank Wirbeleit, Roman Boschke, Martin Gerhardt
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Publication number: 20150187765Abstract: By forming a trench isolation structure after providing a high-k dielectric layer stack, direct contact of oxygen-containing insulating material of a top surface of the trench isolation structure with the high-k dielectric material in shared polylines may be avoided. This technique is self-aligned, thereby enabling further device scaling without requiring very tight lithography tolerances. After forming the trench isolation structure, the desired electrical connection across the trench isolation structure may be re-established by providing a further conductive material.Type: ApplicationFiled: March 11, 2015Publication date: July 2, 2015Inventors: Andy Wei, Roman Boschke, Markus Forsberg
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Publication number: 20150179753Abstract: E-fuses are used in integrated circuits in order to permit real-time dynamic reprogramming of the circuit after manufacturing. An e-fuse is hereby proposed wherein the metal element adapted to be blown upon passage of a current is not comprised of a silicide layer but is rather a metal layer above which a semiconductor layer is formed. A dielectric layer is then formed on the semiconductor layer, in order to prevent metal silicide from forming over the metal layer. The process of manufacturing the e-fuse can be easily integrated in an HKMG manufacturing flow. In particular, fully silicided metal gates may be manufactured in conjunction with the e-fuse, without jeopardizing the correct functioning of the e-fuse.Type: ApplicationFiled: December 20, 2013Publication date: June 25, 2015Applicant: Globalfoundries Inc.Inventors: Roman Boschke, Stefan Flachowsky, Maciej Wiatr, Christian Schippel
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Publication number: 20150179740Abstract: A method for forming a transistor device is disclosed that includes forming a first gate electrode on a substrate, forming a nitride layer, in particular an SiN layer, over the first gate electrode and forming a first strained layer over the nitride layer, in particular the SiN layer. A transistor device is also disclosed that includes a first gate electrode, a nitride layer, in particular an SiN layer, formed over the first gate electrode and a first strained layer formed over the nitride layer, in particular the SiN layer.Type: ApplicationFiled: December 20, 2013Publication date: June 25, 2015Applicant: GLOBAL FOUNDRIES Inc.Inventors: Dina H. Triyoso, Elke Erben, Martin Trentzsch, Peter Moll, Roman Boschke
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Publication number: 20150162414Abstract: When forming field effect transistors, a common problem is the formation of a Schottky barrier at the interface between a metal thin film in the gate electrode and a semiconductor material, typically polysilicon, formed thereupon. Fully silicided gates are known in the state of the art which may overcome this problem. The claimed method proposes an improved fully silicided gate achieved by forming a gate structure including an additional metal layer between the metal gate layer and the gate semiconductor material. A silicidation process can then be optimized so as to form a lower metal silicide layer comprising the metal of the additional metal layer and an upper metal silicide layer forming an interface with the lower metal silicide layer.Type: ApplicationFiled: December 5, 2013Publication date: June 11, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Roman Boschke, Stefan Flachowsky, Elke Erben
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Patent number: 9023712Abstract: By forming a trench isolation structure after providing a high-k dielectric layer stack, direct contact of oxygen-containing insulating material of a top surface of the trench isolation structure with the high-k dielectric material in shared polylines may be avoided. This technique is self-aligned, thereby enabling further device scaling without requiring very tight lithography tolerances. After forming the trench isolation structure, the desired electrical connection across the trench isolation structure may be re-established by providing a further conductive material.Type: GrantFiled: March 20, 2008Date of Patent: May 5, 2015Assignee: Advanced Micro Devices, Inc.Inventors: Andy Wei, Roman Boschke, Markus Forsberg
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Patent number: 9006835Abstract: A semiconductor device includes a first transistor positioned in and above a first semiconductor region, the first semiconductor region having a first upper surface and including a first semiconductor material. The semiconductor device further includes first raised drain and source portions positioned on the first upper surface of the first semiconductor region, the first drain and source portions including a second semiconductor material having a different material composition from the first semiconductor material. Additionally, the semiconductor device includes a second transistor positioned in and above a second semiconductor region, the second semiconductor region including the first semiconductor material. Finally, the semiconductor device also includes strain-inducing regions embedded in the second semiconductor region, the embedded strain-inducing regions including the second semiconductor material.Type: GrantFiled: November 8, 2013Date of Patent: April 14, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Stephan Kronholz, Peter Javorka, Roman Boschke
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Publication number: 20150097252Abstract: When forming field effect transistors according to the gate-first HKMG approach, the cap layer formed on top of the gate electrode had to be removed before the silicidation step, resulting in formation of a metal silicide layer on the surface of the gate electrode and of the source and drain regions of the transistor. The present disclosure improves the manufacturing flow by skipping the gate cap removal process. Metal silicide is only formed on the source and drain regions. The gate electrode is then contacted by forming an aperture through the gate material, leaving the surface of the gate metal layer exposed.Type: ApplicationFiled: October 7, 2013Publication date: April 9, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Stefan Flachowsky, Jan Hoentschel, Roman Boschke
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Patent number: 8962420Abstract: An embedded or buried resistive structure may be formed by amorphizing a semiconductor material and subsequently re-crystallizing the same in a polycrystalline state, thereby providing a high degree of compatibility with conventional polycrystalline resistors, such as polysilicon resistors, while avoiding the deposition of a dedicated polycrystalline material. Hence, polycrystalline resistors may be advantageously combined with sophisticated transistor architectures based on non-silicon gate electrode materials, while also providing high performance of the resistors with respect to the parasitic capacitance.Type: GrantFiled: September 3, 2009Date of Patent: February 24, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Andreas Kurz, Roman Boschke, James Buller, Andy Wei
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Patent number: 8939765Abstract: In sophisticated semiconductor devices, the defect rate that may typically be associated with the provision of a silicon/germanium material in the active region of P-channel transistors may be significantly decreased by incorporating a carbon species prior to or during the selective epitaxial growth of the silicon/germanium material. In some embodiments, the carbon species may be incorporated during the selective growth process, while in other cases an ion implantation process may be used. In this case, superior strain conditions may also be obtained in N-channel transistors.Type: GrantFiled: December 10, 2010Date of Patent: January 27, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Stephan Kronholz, Peter Javorka, Maciej Wiatr, Roman Boschke, Christian Krueger
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Patent number: 8846467Abstract: A method for performing silicidation of a gate electrode is provided that includes forming both a first transistor with a first gate electrode covered by a cap layer and a semiconductor device on the same semiconductor substrate, forming an organic planarization layer (OPL) on the first transistor and the semiconductor device, back etching the OPL such that an upper surface of the OPL is positioned at a level that is below a level of an upper surface of the cap layer, forming a mask layer covering the semiconductor device without covering the first transistor, removing the cap layer while the back-etched OPL and the mask layer are present, and performing silicidation of the first gate electrode.Type: GrantFiled: September 9, 2013Date of Patent: September 30, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Roman Boschke, Stefan Flachowsky, Matthias Kessler
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Publication number: 20140246696Abstract: When forming sophisticated semiconductor devices including N-channel transistors with strain-inducing embedded source and drain semiconductor regions, N-channel transistor performance may be enhanced by selectively growing embedded pure silicon source and drain regions in cavities exposing the silicon/germanium layer of a Si/SiGe-substrate, wherein the silicon layer of the Si/SiGe-substrate may exhibit a strong bi-axial tensile strain. The bi-axial tensile strain may improve both electron and hole mobility.Type: ApplicationFiled: March 4, 2013Publication date: September 4, 2014Applicant: GLOBALFOUNDRIES Inc.Inventors: Stefan Flachowsky, Roman Boschke, Ralf Illgen
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Patent number: 8735241Abstract: Methods for forming CMOS integrated circuit structures are provided, the methods comprising performing a first implantation process for performing at least one of a halo implantation and a source and drain extension implantation into a region of a semiconductor substrate and then forming a stressor region in another region of the semiconductor substrate. Furthermore, a semiconductor device structure is provided, the structure comprising a stressor region embedded into a semiconductor substrate adjacent to a gate structure, the embedded stressor region having a surface differing along a normal direction of the surface from an interface by less than about 8 nm, wherein the interface is formed between the gate structure and the substrate.Type: GrantFiled: January 23, 2013Date of Patent: May 27, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Stefan Flachowsky, Ralf Richter, Roman Boschke