Abstract: Apparatus and associated methods relate to predicting various transient output waveforms at a receiver's output after an initial neural network model is trained by a receiver's transient input waveform and a corresponding transient output waveform. In an illustrative example, the machine learning model may include an adaptive-ordered auto-regressive moving average external input based on neural networks (NNARMAX) model designed to mimic the performance of a continuous time linear equalization (CTLE) mode of the receiver. A Pearson Correlation Coefficient (PCC) score may be determined to select numbers of previous inputs and previous outputs to be used in the neural network model. In other examples, corresponding bathtub characterizations and eye diagrams may be extracted from the predicted transient output waveforms. Providing a machine learning model may, for example, advantageously predict various data patterns without knowing features or parameters of the receiver or related channels.

Abstract: Apparatus and associated methods relate to providing a machine learning methodology that uses the machine learning's own failure experiences to optimize future solution search and provide self-guided information (e.g., the dependency and independency among various adaptation behavior) to predict a receiver's equalization adaptations. In an illustrative example, a method may include performing a first training on a first neural network model and determining whether all of the equalization parameters are tracked. If not all of the equalization parameters are tracked under the first training, then, a second training on a cascaded model may be performed. The cascaded model may include the first neural network model, and training data of the second training may include successful learning experiences and data of the first neural network model. The prediction accuracy of the trained model may be advantageously kept while having a low demand for training data.

Abstract: In one embodiment, an integrated circuit (IC) includes a power distribution network having a first set of power distribution lines connected to a source voltage and a second set of power distribution lines connected to a ground voltage, and a first capacitor. A first variable resistive element is electrically coupled in series with the first capacitor between the first and second sets of power lines of the power distribution network. A control circuit is coupled to the variable resistive element and is configured and arranged to adjust a level of resistance of the first variable resistive element in response to an input signal. The adjustment of the level of resistance adjusts an equivalent series resistance of the power distribution network.

Abstract: Integrated circuits are fabricated with mounted discrete capacitors. Bond pads and land pads are fabricated on a semiconductor wafer. Discrete capacitors are mounted on the semiconductor wafer with flexible adhesive. The flexible adhesive accommodates a difference in thermal expansion between the discrete capacitors and the semiconductor wafer. The land pads are electrically coupled to the electrodes of the discrete capacitors. The semiconductor wafer is separated into multiple semiconductor dice. The semiconductor dice are mounted in respective packages. The bond pads on each semiconductor die are electrically coupled to the interconnect terminals of the respective package.

Abstract: In one embodiment, an integrated circuit (IC) is presented. The IC includes first and second sets of power distribution lines formed in the IC. The IC includes first and second capacitors formed in one or more layers of the IC. A first plurality of vias couple a first input of the first and second capacitors to the first set of power distribution lines, and a second plurality of vias couple a second input of the first and second capacitors to the second set of power distribution lines. The first capacitor and the first plurality of vias and the second plurality of vias coupled thereto having an equivalent series resistance greater than an equivalent series resistance of the second capacitor and the first plurality of vias and the second plurality of vias coupled thereto.

Abstract: In one embodiment, an integrated circuit (IC) is presented. The IC includes first and second sets of power distribution lines formed in the IC. The IC includes first and second capacitors formed in one or more layers of the IC. A first plurality of vias couple a first input of the first and second capacitors to the first set of power distribution lines, and a second plurality of vias couple a second input of the first and second capacitors to the second set of power distribution lines. The first capacitor and the first plurality of vias and the second plurality of vias coupled thereto having an equivalent series resistance greater than an equivalent series resistance of the second capacitor and the first plurality of vias and the second plurality of vias coupled thereto.

Abstract: Apparatus is for processing signals between a tester and devices under test. In one embodiment, the apparatus includes at least one multichip module. Each multichip module has a plurality of micro-electromechanical switches between a set of connectors to the tester and a set of connectors to devices under test. At least one driver is provided to operate each of the micro-electromechanical switches. Other embodiments are also disclosed.

Abstract: Apparatus is for processing signals between a tester and devices under test. In one embodiment, the apparatus includes at least one multichip module. Each multichip module has a plurality of micro-electromechanical switches between a set of connectors to the tester and a set of connectors to devices under test. At least one driver is provided to operate each of the micro-electromechanical switches. A method of processing signals between a tester and devices under test is disclosed. In an embodiment, the method includes connecting the tester and the devices under test with at least one multichip module. Each of the at least one multichip module has a plurality of micro-electromechanical switches between a set of connectors to the tester and a set of connectors to the devices under test. The method includes operating each of the micro-electromechanical switches. Other embodiments are also disclosed.

Abstract: A probe card with an air channel over the active components for cooling the active components on the probe card is provided.

Abstract: A water block heat dissipation on a probe card interface for cooling active components and other devices requiring heat dissipation on the probe card is presented.

Abstract: In one embodiment, a method includes, providing a test program designed to control a circuit test system. The circuit test system has a plurality of test channels, each test channel of which is configured to be selectively coupled to a plurality of sub-channels under control of the test program. The method further includes 1) analyzing the test program to determine what combinations of channels, sub-channels and timing sets are required by the test program, and 2) in response to this analysis, creating a map of which timing sets, for which combinations of channels and sub-channels, should be pre-loaded into pin electronics that correspond to the test channels.

Abstract: In one embodiment, there is disclosed apparatus having a printed circuit board (PCB); a heat sink device for disposition adjacent the bottom surface of the PCB; at least one wiffle tree component disposed adjacent the top surface of the PCB, having a base portion with a plurality of legs extending therefrom; and at least one mechanism to generate a clamping force between the at least one wiffle tree and the top surface of the PCB, and between the bottom surface of the PCB and the heat sink. There is disclosed a method of attaching a printed circuit board (PCB) to a heat sink. In an embodiment, the method includes providing at least one wiffle tree component; disposing one of the at least one wiffle tree component adjacent to the PCB; and securing the one of the at least one wiffle tree component with a fastener. Other embodiments are also disclosed.

Abstract: A paddle board probe card for connecting a device under test with an ATE tester by means of ZIF connectors is presented. The paddle board probe card may include more than one printed circuit board mounted on a probe card in such a manner that the more than one printed circuit boards mate with ZIF connectors on an ATE testhead interface.

Abstract: An inverted mesa quartz crystal oscillator suitable as a time base reference for automatic test equipment is presented. The inverted mesa quartz crystal may be formed by ion beam etching a mesa in a quartz crystal substrate.

Abstract: An epoxy filled via hole in a printed circuit board is presented. The epoxy filled via hole may have metal plating between the epoxy and the via hole walls of the printed circuit board. The epoxy filled via hole may have a land pad directly over the epoxy filling, creating a compact contact area for an ATE interposer.

Abstract: A probe card with an air channel over the active components for cooling the active components on the probe card is provided.

Abstract: A water block heat dissipation on a probe card interface for cooling active components and other devices requiring heat dissipation on the probe card is presented.

Abstract: In one embodiment, a mock wafer for calibrating automated test equipment includes a printed circuit board having a number of interconnect areas, with each interconnect area having a pair of mock die pads that are coupled via a connecting trace. In another embodiment, a method for calibrating automated test equipment (ATE) may include coupling the mock wafer to the ATE, and then causing the ATE to i) index the mock wafer with respect to a test head connector, ii) couple a number of probes or the test head connector to a number of the mock wafer's mock die pads, iii) transmit a test signal between a pair of the probes that are coupled via a pair of mock die pads and connecting trace of the mock wafer, and iv) calibrate a selected signal path or paths of the ATE by recording a characteristic of the transmitted test signal.

Abstract: A paddle board probe card for connecting a device under test with an ATE tester by means of ZIF connectors is presented. The paddle board probe card may include more than one printed circuit board mounted on a probe card in such a manner that the more than one printed circuit boards mate with ZIF connectors on an ATE testhead interface.

Abstract: A low thermal impedance printed circuit board assembly compatible with surface mount assembly reflow solder processes is presented. The low thermal impedance printed circuit board assembly may have filled vias soldered directly to solder balls of the surface mount assembly.