Abstract: A high frequency coaxial through hole via in a multilayer printed circuit board is presented. The high frequency coaxial through hole via may include two traces connected by a plated through hole via and surrounded by more than one ground plane, where the more than one ground planes are capacitively coupled.

Abstract: In one embodiment, there is disclosed apparatus having a printed circuit board (PCB); a heat sink device for disposition adjacent the bottom surface of the PCB; at least one wiffle tree component disposed adjacent the top surface of the PCB, having a base portion with a plurality of legs extending therefrom; and at least one mechanism to generate a clamping force between the at least one wiffle tree and the top surface of the PCB, and between the bottom surface of the PCB and the heat sink. There is disclosed a method of attaching a printed circuit board (PCB) to a heat sink. In an embodiment, the method includes providing at least one wiffle tree component; disposing one of the at least one wiffle tree component adjacent to the PCB; and securing the one of the at least one wiffle tree component with a fastener. Other embodiments are also disclosed.

Abstract: Apparatus is for processing signals between a tester and devices under test. In one embodiment, the apparatus includes at least one multichip module. Each multichip module has a plurality of micro-electromechanical switches between a set of connectors to the tester and a set of connectors to devices under test. At least one driver is provided to operate each of the micro-electromechanical switches. A method of processing signals between a tester and devices under test is disclosed. In an embodiment, the method includes connecting the tester and the devices under test with at least one multichip module. Each of the at least one multichip module has a plurality of micro-electromechanical switches between a set of connectors to the tester and a set of connectors to the devices under test. The method includes operating each of the micro-electromechanical switches. Other embodiments are also disclosed.

Abstract: A low phase noise high speed stabilized time base uses a crystal resonator that operates directly at a desired high frequency of one hundred to several hundred MHz. An inverted mesa AT-cut quartz crystal meets this criteria. To promote frequency stability the crystal and its oscillator circuit are thermally clamped to a convenient temperature that need be only loosely regulated, say, at about room temperature. In an exemplary ATE setting that already provides a water flow heat removal system whose supply side is 26° C.,±0.5° C., a 400 MHz inverted mesa AT-cut crystal is simply given its own loop within that water supply. Other temperature stabilization techniques for loose regulation, such as Peltier cells, may be used. The result is a high frequency time base having adequate frequency accuracy and stability, but with the extremely low timing jitter of just the crystal resonator, since there is no contributory timing jitter from a frequency multiplying PLL.

Abstract: In one embodiment, a method includes, providing a test program designed to control a circuit test system. The circuit test system has a plurality of test channels, each test channel of which is configured to be selectively coupled to a plurality of sub-channels under control of the test program. The method further includes 1) analyzing the test program to determine what combinations of channels, sub-channels and timing sets are required by the test program, and 2) in response to this analysis, creating a map of which timing sets, for which combinations of channels and sub-channels, should be pre-loaded into pin electronics that correspond to the test channels.

Abstract: A DUT contactor integrated into a DUT or probe board is presented. The DUT contactor integrated into a DUT/probe board may comprise a raised metallization contact layer on one surface of a multi-layer printed circuit board.

Abstract: In one embodiment, a mating circuit assembly is coupled and decoupled to a system by 1) mechanically and electrically coupling at least a first interposer, mounted on at least one of first and second substrates, to the mating circuit assembly. The mechanical and electrical coupling is accomplished using at least first and second spring mechanisms, with the first and second spring mechanisms being mounted between the connector housing and respective ones of the first and second substrates. At least one of the first and second substrates transmits signals between the first interposer and the system. The first interposer is electrically and mechanically decoupled from the mating circuit assembly by creating a vacuum between the connector housing and at least one of the first and second substrates. Other embodiments are also disclosed.

Abstract: A UV light source and a specially adapted vacuum fitting for visualizing and non-contact cleaning of dust contaminants from XZIF connections and test head electronics in a clean room environment is presented.

Abstract: A parallel calibration system for an electronic circuit tester comprises test and measurement electronics, a test fixture coupled to the test and measurement electronics, the test fixture comprising clock reference circuitry and clock distribution circuitry, a device under test interface, and a plurality of calibration boards coupled to the device under test interface, wherein the plurality of calibration boards and the clock distribution circuitry simultaneously test the signal paths of a plurality of test channels.

Abstract: In one embodiment, a mock wafer for calibrating automated test equipment includes a printed circuit board having a number of interconnect areas, with each interconnect area having a pair of mock die pads that are coupled via a connecting trace. In another embodiment, a method for calibrating automated test equipment (ATE) may include coupling the mock wafer to the ATE, and then causing the ATE to i) index the mock wafer with respect to a test head connector, ii) couple a number of probes or the test head connector to a number of the mock wafer's mock die pads, iii) transmit a test signal between a pair of the probes that are coupled via a pair of mock die pads and connecting trace of the mock wafer, and iv) calibrate a selected signal path or paths of the ATE by recording a characteristic of the transmitted test signal.

Abstract: A parallel calibration system for an electronic circuit tester comprises test and measurement electronics, a test fixture coupled to the test and measurement electronics, the test fixture comprising clock reference circuitry and clock distribution circuitry, a device under test interface, and a plurality of calibration boards coupled to the device under test interface, wherein the plurality of calibration boards and the clock distribution circuitry simultaneously test the signal paths of a plurality of test channels.

Abstract: Systems and methods for calibrating the timing of electronic circuit testers and verifying the timing calibration of electronic circuit testers are described. In some embodiments, a calibration reference signal is transmitted from the test head directly through the load board interface, rather than through external instruments, so that timing errors associated with external wires and cables may be avoided. The timing calibration and timing calibration verification functionality is provided on a single calibration board, thereby reducing the calibration set-up time relative to conventional robot-based calibrators. In addition, a high pin count electronic circuit testers may be calibrated by a calibration board that is configured to calibrate one subset of the test channels at a time.

Abstract: Systems and methods for calibrating the timing of electronic circuit testers and verifying the timing calibration of electronic circuit testers are described. In some embodiments, a calibration reference signal is transmitted from the test head directly through the load board interface, rather than through external instruments, so that timing errors associated with external wires and cables may be avoided. The timing calibration and timing calibration verification functionality is provided on a single calibration board, thereby reducing the calibration set-up time relative to conventional robot-based calibrators. In addition, a high pin count electronic circuit testers may be calibrated by a calibration board that is configured to calibrate one subset of the test channels at a time.