Patents by Inventor Ron Zhang

Ron Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10611204
    Abstract: Systems and methods for controlling one or more tractive assemblies of a vehicle responsive to a disabling event. A sensor is arranged to detect one or more conditions of a tractive element indicative of the functionality of the tractive element. The sensor generates data corresponding to the detected conditions. The tractive element is coupled to a frame of the vehicle and configured to support a portion of the weight of the vehicle. When the tractive element is determined to not be functioning properly, control signal(s) for an actuator are generated to control a distance between the tractive element and the frame. The control signal(s) cause the tractive element to be effectively raised from a support surface for the vehicle.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: April 7, 2020
    Assignee: Oshkosh Defense, LLC
    Inventors: Ron Zhang, David Hansen, Deepak Shukla, Aaron Rositch
  • Publication number: 20190278035
    Abstract: An optical transceiver may include a circuit board, lasers, and a PLC including optical multiplexers and demultiplexers. The PLC may be coupled to fiber optic lines at a forward edge of the PLC, with a rear edge of the PLC receiving light for transmission generated by the lasers. Light received at the forward edge of the PLC may be demultiplexed into data channels and routed to a top surface of the PLC for optoelectronic conversion by photodetectors. In some embodiments each data channel is routed into a corresponding plurality of waveguides, with each of the corresponding plurality of waveguides providing light to the same photodetector. In some embodiments at least some receive side electronic circuitry, other than photodetectors, is stacked on top of the PLC.
    Type: Application
    Filed: March 11, 2019
    Publication date: September 12, 2019
    Inventors: Bardia Pezeshki, Hendrick Bulthuis, Ramsey Selim, Andrew Grant, Lucas Soldano, Owen Shea, Josef Wendland, Jamie Stokes, Suresh Rangarajan, Josh Oen, Ron Zhang, Rob Kalman, Drew Lundsten
  • Patent number: 9991231
    Abstract: An apparatus relates generally to an integrated circuit package. In such an apparatus, a package substrate has a first plurality of via structures extending from a lower surface of the package substrate to an upper surface of the package substrate. An die has a second plurality of via structures extending to a lower surface of the die. The lower surface of the die faces the upper surface of the package substrate in the integrated circuit package. The package substrate does not include a redistribution layer. The die and the package substrate are coupled to one another.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: June 5, 2018
    Assignee: Invensas Corporation
    Inventors: Charles G. Woychik, Cyprian Emeka Uzoh, Ron Zhang, Daniel Buckminster, Guilian Gao
  • Publication number: 20170033088
    Abstract: An apparatus relates generally to an integrated circuit package. In such an apparatus, a package substrate has a first plurality of via structures extending from a lower surface of the package substrate to an upper surface of the package substrate. An die has a second plurality of via structures extending to a lower surface of the die. The lower surface of the die faces the upper surface of the package substrate in the integrated circuit package. The package substrate does not include a redistribution layer. The die and the package substrate are coupled to one another.
    Type: Application
    Filed: August 11, 2016
    Publication date: February 2, 2017
    Applicant: Invensas Corporation
    Inventors: Charles G. Woychik, Cyprian Emeka Uzoh, Ron Zhang, Daniel Buckminster, Guilian Gao
  • Patent number: 9418924
    Abstract: An apparatus relates generally to an integrated circuit package. In such an apparatus, a package substrate has a first plurality of via structures extending from a lower surface of the package substrate to an upper surface of the package substrate. An die has a second plurality of via structures extending to a lower surface of the die. The lower surface of the die faces the upper surface of the package substrate in the integrated circuit package. The package substrate does not include a redistribution layer. The die and the package substrate are coupled to one another.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: August 16, 2016
    Assignee: Invensas Corporation
    Inventors: Charles G. Woychik, Cyprian Emeka Uzoh, Ron Zhang, Daniel Buckminster, Guilian Gao
  • Publication number: 20150270209
    Abstract: An apparatus relates generally to an integrated circuit package. In such an apparatus, a package substrate has a first plurality of via structures extending from a lower surface of the package substrate to an upper surface of the package substrate. An die has a second plurality of via structures extending to a lower surface of the die. The lower surface of the die faces the upper surface of the package substrate in the integrated circuit package. The package substrate does not include a redistribution layer. The die and the package substrate are coupled to one another.
    Type: Application
    Filed: March 20, 2014
    Publication date: September 24, 2015
    Applicant: INVENSAS CORPORATION
    Inventors: Charles G. WOYCHIK, Cyprian Emeka UZOH, Ron ZHANG, Daniel BUCKMINSTER, Guilian GAO
  • Publication number: 20140225208
    Abstract: Some implementations provide a die that includes a magnetoresistive random access memory (MRAM) cell array that includes several MRAM cells. The die also includes a first ferromagnetic layer positioned above the MRAM cell array, a second ferromagnetic layer positioned below the MRAM cell array, and several vias positioned around at least one MRAM cell. The via comprising a ferromagnetic material. In some implementations, the first ferromagnetic layer, the second ferromagnetic layer and the several vias define a magnetic shield for the MRAM cell array. The MRAM cell may include a magnetic tunnel junction (MTJ). In some implementations, the several vias traverse at least a metal layer and a dielectric layer of the die. In some implementations, the vias are through substrate vias. In some implementations, the ferromagnetic material has high permeability and high B saturation.
    Type: Application
    Filed: February 26, 2013
    Publication date: August 14, 2014
    Applicant: Qualcomm Incorporated
    Inventors: Shiqun Gu, Ron Zhang, Vidhya Ramachandran, Dong Wook Kim
  • Publication number: 20140061744
    Abstract: A capacitor includes a semiconductor substrate. The capacitor also includes a first terminal having a fin disposed on a surface of the semiconductor substrate. The capacitor further includes a dielectric layer disposed onto the fin. The capacitor still further includes a second terminal having a FinFET compatible high-K metal gate disposed proximate and adjacent to the fin.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 6, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Ron Zhang, Lew G. Chua-Eoan, Shiqun Gu
  • Patent number: 7571059
    Abstract: A mechanism is disclosed for determining an accelerated test for a device. The method comprises calculating an estimated amount of damage that an element of the device would suffer if the device were operated under a set of specified conditions over a certain period of time (e.g., expected lifetime of the device). The method further comprises determining an accelerated test to which to subject the element in order to cause the element to suffer an actual amount of damage that is approximately equal to the estimated amount of damage. The accelerated test may be an accelerated test cycle, such as an accelerated temperature cycle.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: August 4, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Ron Zhang, Bidyut Sen
  • Publication number: 20080004826
    Abstract: A mechanism is disclosed for determining an accelerated test for a device. The method comprises calculating an estimated amount of damage that an element of the device would suffer if the device were operated under a set of specified conditions over a certain period of time (e.g., expected lifetime of the device). The method further comprises determining an accelerated test to which to subject the element in order to cause the element to suffer an actual amount of damage that is approximately equal to the estimated amount of damage. The accelerated test may be an accelerated test cycle, such as an accelerated temperature cycle.
    Type: Application
    Filed: June 28, 2006
    Publication date: January 3, 2008
    Inventors: Ron Zhang, Bidyut Sen
  • Patent number: 6944025
    Abstract: An electromagnetic shielding structure is provided for a microprocessor or other electronic device that emits electromagnetic radiation. The structure includes a heat sink with an integrally formed depending skirt, and a conductive, compressible polymer is applied to a bottom surface of the skirt. The bottom surface mounts against a socket carried on a circuit board and is electrically coupled to a ground plane of the circuit board. The socket substantially surrounds the microprocessor in at least two dimensions (e.g. length and width). A shielding structure is formed at least partly by the heat sink, the socket and the ground plane.
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: September 13, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: David M. Hockanson, Ron Zhang, George Zacharisen, Deviprasad Malladi
  • Publication number: 20040037042
    Abstract: An electromagnetic shielding structure is provided for a microprocessor or other electronic device that emits electromagnetic radiation. The structure includes a heat sink with an integrally formed depending skirt, and a conductive, compressible polymer is applied to a bottom surface of the skirt. The bottom surface mounts against a socket carried on a circuit board and is electrically coupled to a ground plane of the circuit board. The socket substantially surrounds the microprocessor in at least two dimensions (e.g. length and width). A shielding structure is formed at least partly by the heat sink, the socket and the ground plane.
    Type: Application
    Filed: August 19, 2003
    Publication date: February 26, 2004
    Inventors: David M. Hockanson, Ron Zhang, George Zacharisen, Deviprasad Malladi
  • Patent number: 6243264
    Abstract: A heat sink assembly includes a heat sink, a circuit board and an integrated circuit package. The package is located between the heat sink and the circuit board and attached to a die attach area of the circuit board. A heat sink retainer attached to the heat sink has a base section located adjacent to the circuit board directly opposite the die attach area. The retainer presses the heat sink down uniformly on the package. Further, the downward force applied to the heat sink is countered by an equal upward force applied by the base section of the retainer on the circuit board. Since the base section is located directly opposite the die attach area, the upward force is transferred from the base section directly back to the heat sink without imparting any bending force on the circuit board.
    Type: Grant
    Filed: August 30, 1999
    Date of Patent: June 5, 2001
    Assignee: Sun Microsystems, Inc.
    Inventors: Vernon P. Bollesen, Ron Zhang, James A. Jones