Patents by Inventor Ronald A. Powell

Ronald A. Powell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050056423
    Abstract: Methods are provided for removing filter cake containing a bridging agent soluble in a carboxylic acid salt from a formation fluids producing zone penetrated by a well bore. The methods basically comprise the steps of introducing in an aqueous carrier liquid a carboxylic acid ester and a base for slowly catalyzing the hydrolysis of the ester and forming a carboxylic acid salt therewith into the producing zone, and allowing the base to catalyze the hydrolysis of the carboxylic acid ester to form the carboxylic acid salt so that the carboxylic acid salt dissolves the bridging agent and the filter cake is removed.
    Type: Application
    Filed: September 11, 2003
    Publication date: March 17, 2005
    Inventors: Bradey Todd, Ronald Powell
  • Publication number: 20050034865
    Abstract: Improved methods and compositions for degrading filter cake deposited in a subterranean formation are provided. These methods and compositions utilize particulates coated with acid-releasing degradable material wherein the released acid is used to degrade a filter cake.
    Type: Application
    Filed: August 14, 2003
    Publication date: February 17, 2005
    Inventors: Bradley Todd, Ronald Powell
  • Publication number: 20050032152
    Abstract: This invention relates to enzyme compositions and methods of using these enzyme compositions, inter alia, to degrade succinoglycan. In one embodiment, the present invention provides a method of degrading succinoglycan comprising contacting the succinoglycan with an enzyme composition that comprises enzymes that are capable of degrading the linkages between sugar moieties of the succinoglycan.
    Type: Application
    Filed: August 5, 2003
    Publication date: February 10, 2005
    Inventors: Ronald Powell, Bradley Todd
  • Patent number: 6790773
    Abstract: A process and structure are provided that allows electroplating to fill sub-micron, high aspect ratio features using a non-conformal conductive layer between the dielectric layer and the platability layer. The conductive layer is a relatively thick layer overlying the planar surface of the wafer and the bottom of the features to be filled. Little or no material of the conductive layer is formed on the feature sidewalls. The thick conductive layer on the field provides adequate conductivity for uniform electroplating, while the absence of significant conductive material on the sidewalls decreases the aspect ratio of the feature and makes void-free filling easier to accomplish with electroplating. Further, the absence of significant material on the sidewalls allows a thicker barrier layer to be formed for higher reliability.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: September 14, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: John S. Drewery, Ronald A. Powell
  • Publication number: 20040118812
    Abstract: Methods are described for removing a material from a substrate by dissolving an etchant into a solvent to form a solution; and exposing the substrate to the solution so that the etchant in the solution removes material from the substrate; wherein during the exposure the solution is maintained in a supercritical or near-supercritical phase. The described methods can include additional steps, such as exposing a precursor of the material to a reagent to form the material, and depositing a second material onto the substrate after removing the material from the substrate.
    Type: Application
    Filed: August 7, 2003
    Publication date: June 24, 2004
    Inventors: James J. Watkins, Patrick A. Van Cleemput, Ronald Powell
  • Patent number: 6709557
    Abstract: A mosaic or inlaid sputter target design suitable for conventional planar magnetron deposition, RF ionized physical vapor deposition, HCM ionized PVD, ionized metal plasma (IMP) deposition, or self-ionized plasma (SIP) deposition of multi-component alloys for use in integrated circuit metallization. Inlays are inserted within a planar sputter target in the shape of wedges, wires, or buttons to achieve uniform deposition of films on semiconductor substrates during sputtering. Metal alloy strips within a three-dimensional HCM target achieve the same uniform deposition. The deposition leads to the production of CuAl, CuBe, CuB, CuCd, CuCo, CuCr, CuIn, CuPd, CuSn, CuTa, CuTi, CuZr or CuZn alloy films deposited on the wafer. Non-copper films may also be deposited. The inlay-target adjoining surfaces may be machine stepped or tapered to limit wicking from the target backing material.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: March 23, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: Sridhar K. Kailasam, Ronald A. Powell, E. Derryck Settles
  • Patent number: 6607982
    Abstract: The present invention pertains to systems and methods for simultaneously producing a diffusion barrier and a seed layer used in integrated circuit metallization. This is achieved by initially depositing copper-magnesium (Cu—Mg) alloys with relatively high levels of Mg (>10 atomic %, which is equivalent to about >4 weight %). After the alloys are deposited, they self-form a magnesium oxide (MgO) based barrier layer at the substrate interface, thus eliminating the need for a separate operation for barrier deposition. The migration of Mg to the substrate interface leaves the remainder of the film relatively pure Cu.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: August 19, 2003
    Assignee: Novellus Systems, Inc.
    Inventors: Ronald A. Powell, Sridhar K. Kailasam, E. Derryck Settles, Larry R. Lane
  • Patent number: 6589887
    Abstract: The present invention pertains to methods for forming metal-derived layers on substrates. Preferred methods apply to integrated circuit fabrication. In particular, selective methods may be used to form diffusion barriers on partially fabricated integrated circuits. In one preferred method, a wafer is heated and exposed to a metal vapor. Under specific conditions, the metal vapor reacts with dielectric surfaces to form a diffusion barrier, but does not react with metal surfaces. Thus, methods of the invention form diffusion barriers that selectively protect dielectric surfaces but leave metal surfaces free of diffusion barrier.
    Type: Grant
    Filed: October 11, 2001
    Date of Patent: July 8, 2003
    Assignee: Novellus Systems, Inc.
    Inventors: Jeremie Dalton, Ronald A. Powell, Sridhar K. Kailasam, Sasangan Ramanathan
  • Patent number: 6541374
    Abstract: The present invention pertains to methods for forming diffusion barrier layers in the context of integrated circuit fabrication. Methods of the invention allow selective deposition of a metal-nitride barrier layer material on a partially fabricated integrated circuit having exposed conductor and dielectric regions and conversion of the metal-nitride barrier material into an effective diffusion barrier layer having low via resistance. In a preferred method using TiN, differential morphology in a single barrier layer deposition is achieved by controlling CVD process conditions. It is believed that the absolute amount of TiN deposited on the conductor is not reduced, but the morphology of is changed so that there is little or no increase in the via resistance after barrier formation. The invention also pertains to novel integrated circuit structures resulting from application of the described methods.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: April 1, 2003
    Assignee: Novellus Systems, Inc.
    Inventors: Tarek Suwwan de Felipe, Michal Danek, Erich Klawuhn, Ronald A. Powell
  • Patent number: 6525829
    Abstract: A method and apparatus for performing reflectometry using a specific wavelength or a small number of specific wavelengths within a spectral range to detect the presence of a copper oxide film on a substrate or to measure the film thickness is described. A method for analyzing reflectivity data to obtain film thickness is also described. Using the described method and apparatus, reflectometry can be performed using only one or two wavelengths of light so that simple photodiode detectors may be used instead of a complex and costly spectrometer (although a spectrometer may be used to detect the reflected light). Therefore, the described invention can provide in-situ or vacuum integrated metrology with simple, low-cost hardware. Finally, the described method does not require detailed curve fitting and thus the necessary thickness data can be acquired rapidly.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: February 25, 2003
    Assignee: Novellus Systems, Inc.
    Inventors: Ronald A. Powell, E. Derryck Settles, Sridhar K. Kailasam
  • Patent number: 6464779
    Abstract: This invention pertains to systems and methods for atomic layer chemical vapor deposition. More specifically, the invention pertains to methods for copper atomic layer chemical vapor deposition, particularly to deposit a seed layer prior to the electrochemical Cu fill operation in integrated circuit fabrication. It also pertains to apparatus modules for performing such deposition.
    Type: Grant
    Filed: January 19, 2001
    Date of Patent: October 15, 2002
    Assignee: Novellus Systems, Inc.
    Inventors: Ronald A. Powell, James A. Fair
  • Publication number: 20020039625
    Abstract: This invention provides an apparatus and method for injecting gas within a plasma reactor and tailoring the distribution of an active species generated by the remote plasma source over the substrate or wafer. The distribution may be made more or less uniform, wafer-edge concentrated, or wafer-center concentrated. A contoured plate or profiler is provided for modifying the distribution. The profiler is an axially symmetric plate, having a narrow top end and a wider bottom end, shaped to redistribute the gas flow incident upon it. The profiler is situated below an input port within the plasma reactor chamber and above the wafer. The method for tailoring the distribution of the active species over the substrate includes predetermining the profiler diameter and adjusting the profiler height over the substrate.
    Type: Application
    Filed: July 2, 2001
    Publication date: April 4, 2002
    Applicant: Novellus Systems, Inc.
    Inventors: Ronald A. Powell, Gabriel I. Font-Rodriguez, Simon Selitser, Emerson Derryck Settles
  • Publication number: 20020029747
    Abstract: This invention provides an apparatus and method for injecting gas within a plasma reactor and tailoring the distribution of an active species generated by the remote plasma source over the substrate or wafer. The distribution may be made more or less uniform, wafer-edge concentrated, or wafer-center concentrated. A contoured plate or profiler is provided for modifying the distribution. The profiler is an axially symmetric plate, having a narrow top end and a wider bottom end, shaped to redistribute the gas flow incident upon it. The profiler is situated below an input port within the plasma reactor chamber and above the wafer. The method for tailoring the distribution of the active species over the substrate includes predetermining the profiler diameter and adjusting the profiler height over the substrate.
    Type: Application
    Filed: July 2, 2001
    Publication date: March 14, 2002
    Applicant: Novellus Systems, Inc.
    Inventors: Ronald A. Powell, Gabriel I. Font-Rodriguez, Simon Selitser, Emerson Derryck Settles
  • Patent number: 6319842
    Abstract: Non-volatile and oxide residues that form during semiconductor processing are removed from the semiconductor structure in a two-stage process. An inert gas and a reducing gas are introduced to the reactor. In the first stage, the non-volatile contaminants are sputtered from the semiconductor structure by creating a plasma to ionize the inert gas. The power applied to the plasma is preferably high enough to give the ions of the inert gas a high degree of directionality as they approach the structure. The first stage is continued until the non-volatile contaminants have been sufficiently removed from the structure. In the second stage, the power is reduced and the reducing gas (e.g., hydrogen) reacts with the oxides (e.g., copper oxide) to form elemental metal and water vapor. During the second stage there is no appreciable sputtering, and therefore the damage to the structure is limited as compared with processes that use sputtering and reduction simultaneously.
    Type: Grant
    Filed: January 2, 2001
    Date of Patent: November 20, 2001
    Assignee: Novellus Systems Incorporated
    Inventors: Mukul Khosla, Lap Tam, Ronald A. Powell, Ronald D. Allen, Robert T. Rozbicki, Erich Klawuhn, E. Derryck Settles
  • Patent number: 5118200
    Abstract: Remote measurement of temperature of a process chamber provided with a substrate exhibiting a temperature dependent band gap which substrate is illuminated by a source of continuous spectrum light with a spectrum which overlaps the band gap edge of the substrate. The light which exits the substrate is focused by a lens and is picked up by a fiber optic which takes it to a spectrometer where the spectrum is analyzed to ascertain the intensity versus wavelength histograph for exit rays in the wavelength region of the equivalent band gap of the substrate. The wavelength at the point of infection in the region of band gap edge of the substrate in the histograph of the wavelength versus intensity characteristic of exit rays determines the real time substrate temperature from predetermined calibration data which correlates the wavelength at the point of inflection to actual temperature of the substrates.
    Type: Grant
    Filed: June 13, 1990
    Date of Patent: June 2, 1992
    Assignee: Varian Associates, Inc.
    Inventors: Dimitry M. Kirillov, Ronald A. Powell
  • Patent number: 4807994
    Abstract: A method of mapping implanted ion dose uniformity is disclosed in which wafers of polysilicon-on-silicon or polysilicon-on-oxidized-silicon are implanted with the ion dose to be mapped and then scanned in a spectrophotmeter using monochromatic radiation. An interference spectral technique is used to achieve improved sensitivity while preserving thermal and electrical properties close to those of actual devices.
    Type: Grant
    Filed: November 19, 1987
    Date of Patent: February 28, 1989
    Assignee: Varian Associates, Inc.
    Inventors: Susan B. Felch, Ronald A. Powell
  • Patent number: 4764026
    Abstract: A probe having four spring-loaded tips contacts the backside of a semiconductor wafer in a processing machine. A current is induced across the outer tips and a voltage proportional to the sheet resistance of the wafer is measured across the inner tips. Wafer thickness is used to convert sheet resistance to bulk resistivity. Data on resistivity as a function of temperature is used to determine wafer temperature.
    Type: Grant
    Filed: July 7, 1986
    Date of Patent: August 16, 1988
    Assignee: Varian Associates, Inc.
    Inventors: Ronald A. Powell, Susan B. Felch
  • Patent number: 4661177
    Abstract: Doping of a semiconductor wafer is accomplished by placing the wafer in close proximity to a solid planar dopant source and rapidly heating the combination to a high temperature for a short time in a rapid thermal processing apparatus.
    Type: Grant
    Filed: October 8, 1985
    Date of Patent: April 28, 1987
    Assignee: Varian Associates, Inc.
    Inventor: Ronald A. Powell
  • Patent number: 4522845
    Abstract: Multichromatic radiation is applied rapidly to silicon or polysilicon placed in contact with a silicide-forming metal to form metal silicide having low resistivity without deleterious later diffusion of dopants in adjacent single crystal or polysilicon. The radiation is applied to a metal deposited on silicon or to a metal codeposited with or to silicide deposited from a metal-Si composite target. The temperatures preferably rise to between 600.degree. C. and 1200.degree. C. and the total heating periods are less than about one minute, with 10 to 30 seconds being typical.
    Type: Grant
    Filed: June 20, 1983
    Date of Patent: June 11, 1985
    Assignee: Varian Associates, Inc.
    Inventors: Ronald A. Powell, Ronald T. Fulks
  • Patent number: D248581
    Type: Grant
    Filed: August 10, 1976
    Date of Patent: July 18, 1978
    Inventor: Ronald Powell