Patents by Inventor Ronald E. Lange

Ronald E. Lange has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6581125
    Abstract: A computer system includes a host processor, a first PCI bus, a second PCI bus and a bus bridge. The first PCI bus is coupled with the host processor. The bus bridge interconnects the first and second PCI buses. The bus bridge includes a first portion having a first bridge memory, a second portion having a second bridge memory, and a latency inducing serial bus interconnecting the first portion and the second portion. A method is also taught.
    Type: Grant
    Filed: May 14, 1999
    Date of Patent: June 17, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Ronald E. Lange, David Ross Evoy
  • Patent number: 6457091
    Abstract: A computer system includes a host processor, a first PCI bus, a second PCI bus and a PCI-to-PCI bridge. The first PCI bus is coupled with the host processor. The PCI-to-PCI bridge interconnects the first and second PCI buses. The PCI-to-PCI bridge includes a first portion and a second portion. The first portion includes a first configuration register and the second portion includes a second configuration register. A method is also taught.
    Type: Grant
    Filed: May 14, 1999
    Date of Patent: September 24, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Ronald E. Lange, David Ross Evoy
  • Patent number: 5894581
    Abstract: In order to reduce the size of the memory employed to store firmware, the firmware is written in virtual control words which are then reduced by allotting them to a primary control word memory and at least one secondary control word memory which is addressed by a field in the primary control word memory. A virtual set of secondary control words are each divided into a plurality of fields, and each field of each secondary virtual control word is marked as guarded or "don't care". If a field is marked as "don't care", the function represented by the virtual control word will perform properly no matter what the content of that field. Virtual control word pairs are then examined to ascertain if they can be combined into a single control word.
    Type: Grant
    Filed: April 15, 1993
    Date of Patent: April 13, 1999
    Assignee: Bull HN Information Systems Inc.
    Inventors: Wilbur L. Stewart, Richard L. Demers, Ronald E. Lange, Lowell D. McCulley
  • Patent number: 5644761
    Abstract: In order to efficiently undertake the micro-steps required to execute an extended instruction in a central processing unit, a main sequence controller and a separate basic operations controller having its own sequencer and the ability to run semi-autonomously are provided. Normally, the main sequence controller determines the operation of the basic operations controller, but, in the case of execution of, for example, a multi-word instruction requiring extended basic operations, the basic operations controller temporarily takes control over the main controller until the extended basic operations have been completed. The result is a relatively simple sequencer that supports tight micro-coded functions where many of the sequence decisions can be predetermined.
    Type: Grant
    Filed: June 5, 1992
    Date of Patent: July 1, 1997
    Assignee: Bull HN Information Systems Inc.
    Inventors: Ronald W. Yoder, Ronald E. Lange, William A. Shelly, Russell W. Guenthner, Richard L. Demers
  • Patent number: 5568622
    Abstract: Method and apparatus to reduce the number of control words stored in a read only control store of a microprogrammed unit of the CPU of a large scale computer. A set of control fields are required to control the active elements of the unit to cause the unit to execute a large number of different basic operations. Typically the required set of control fields are included in control words stored in a control store controlling the unit during the execution of a basic operation. Obtaining some of the set of required control fields from other sources available within the unit results in a significant reduction in the number of control words stored in the control store without reducing the functionality of the unit.
    Type: Grant
    Filed: April 15, 1993
    Date of Patent: October 22, 1996
    Assignee: Bull HN Information Systems Inc.
    Inventors: Wilbur Stewart, Richard L. Demers, Ronald E. Lange
  • Patent number: 5557737
    Abstract: In order to gather, store temporarily and efficiently deliver (if needed) safestore information in a fault tolerant central processing unit having data manipulation circuitry including a plurality of software visible registers, a shadow set of the software visible registers are used in conjunction with shadowing and packing circuitry for copying the contents of the software visible registers, after a data manipulation operation, into the shadow set after the validity of such contents have been verified. In the event of a detected fault in a data manipulation operation, the contents of the shadow set, which will be the last valid set immediately before the error was detected, are transferred back to the software visible registers to institute recovery at the point in the data manipulation immediately prior to that at which the error was detected.
    Type: Grant
    Filed: June 13, 1994
    Date of Patent: September 17, 1996
    Assignee: Bull HN Information Systems Inc.
    Inventors: John E. Wilhite, Ronald E. Lange
  • Patent number: 5553232
    Abstract: In order to gather, store temporarily and efficiently deliver (if needed) safestore information in a fault tolerant central processing unit having data manipulation circuitry including a plurality of software visible registers, a shadow set of the software visible registers are used in conjunction with shadowing and packing circuitry for copying the contents of the software visible registers, after a data manipulation operation, into the shadow set after the validity of such contents have been verified. In the event of a detected fault in a data manipulation operation, the contents of the shadow set, which will be the last valid set immediately before the error was detected, are transferred back to the software visible registers to institute recovery at the point in the data manipulation immediately prior to that at which the error was detected.
    Type: Grant
    Filed: June 13, 1994
    Date of Patent: September 3, 1996
    Assignee: Bull HN Informations Systems Inc.
    Inventors: John E. Wilhite, Ronald E. Lange
  • Patent number: 5515529
    Abstract: In order to validate data manipulation results in a CPU which incorporates duplicate BPUs for integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation operations, a first BPU transfers to cache storage only the even bits of a given data manipulation result, and a second BPU correspondingly transfers to cache storage only the odd bit information of the result. One BPU segregates the even bits of the result, adds parity information and sends the even bits and parity information to the cache unit. Similarly, the second BPU segregates the odd bits of the result, adds parity information and sends the odd bits and parity information to the cache unit. In the cache unit, the even and odd bit information are separately parity checked before storage into cache memory. If a parity error is observed in either set of information, an error signal is issued to institute appropriate remedial action.
    Type: Grant
    Filed: March 25, 1994
    Date of Patent: May 7, 1996
    Inventors: William A. Shelly, Ronald E. Lange, Donald C. Boothroyd
  • Patent number: 5507000
    Abstract: In a central processor incorporating at least one co-processor, such as a floating point arithmetic co-processor, in addition to a basic arithmetic logic unit, the problem of rationalizing the contents of the accumulator and supplementary accumulator registers without the burden of speed penalties is addressed and solved. This is achieved by providing input/output access to a common register file and by switching control of the register file to the proper processing unit appropriately. A single, shared accumulator register and a single, shared supplementary accumulator register are included in the stack along with other sharable registers such as address modification registers. Thus, the contents of the accumulator register and the supplementary accumulator register are always up-to-date and available to all processing units in the central processor without the need for first carrying out rationalization steps.
    Type: Grant
    Filed: September 26, 1994
    Date of Patent: April 9, 1996
    Assignee: Bull HN Information Systems Inc.
    Inventors: Wilbur L. Stewart, Ronald E. Lange, Richard L. Demers, Jeffrey D. Weintraub
  • Patent number: 5495579
    Abstract: In order to validate data manipulation results in a CPU which incorporates duplicate basic processing units or integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation to obtain first and second data manipulation results, which should be identical, and a cache unit for receiving data manipulation results from both BPUs and for transferring specified information words simultaneously to both BPUs upon request. These operations are controlled by cache interface control signals identically generated in each BPU. In each BPU, the control signals are arranged into first and second groups which are nominally identical. The first control signal group is transmitted to the cache unit from one BPU while the second control group is transmitted to the cache unit from the other BPU. In each BPU, parity is generated for each control group separately.
    Type: Grant
    Filed: March 25, 1994
    Date of Patent: February 27, 1996
    Assignee: Bull HN Information Systems Inc.
    Inventors: William A. Shelly, Ronald E. Lange, Donald C. Boothroyd
  • Patent number: 5367699
    Abstract: In order to obtain precise submodel control in a central processing unit, there is provided a subcounter which is controlled to count up from a beginning count as an instruction is executed and to count back down at the same rate to the reference count to obtain an effective delay before processing of the next instruction to be processed during normal program execution is started. Instruction transfer and decoding of the new instruction entering the pipeline is inhibited until the subcounter's most significant bit ("sign bit") changes state. If the subcounter is allowed to count during the entire count up and count down periods, a derated mode of 1/2 is achieved. To obtain other fractions, the subcounter is controlled to count periodically during one count direction period and to count full time during the other count direction period.
    Type: Grant
    Filed: November 26, 1991
    Date of Patent: November 22, 1994
    Assignee: Bull HN Information Systems Inc.
    Inventors: Ronald E. Lange, Russell W. Guenthner, Leonard Rabins
  • Patent number: 5276862
    Abstract: In order to gather, store temporarily and deliver (if needed) central processor safestore information, a multiphase clock is employed to capture (one full clock cycle behind) the safestore information which typically includes all software visible registers in all (or selected) data manipulation chips of the CPU by routing the safestore information through temporary storage (under the influence of the multiphase clock) in a cache data array and into a special purpose XRAM module. Thus, upon the sensing of a fault, valid safestore information is available in the XRAM for analysis and, if appropriate, resumption of operation at a sequential point just previous to that at which the fault occurred.
    Type: Grant
    Filed: April 9, 1991
    Date of Patent: January 4, 1994
    Assignee: Bull HN Information Systems Inc.
    Inventors: Lowell D. McCulley, Russell W. Guenthner, Clinton B. Eckard, Leonard Rabins, William A. Shelly, Ronald E. Lange, David S. Edwards
  • Patent number: 5263034
    Abstract: In order to provide efficient error detection in a central processor's Basic Processing Unit (BPU) including an AX (address and execution) module, a DN (decimal numeric) module and an FP (floating point) module, each module is provided redundantly in a master/slave pair, and the local result of data manipulation operations performed in each pair are compared for identity before the results are validated for subsequent use in the central processor.
    Type: Grant
    Filed: October 9, 1990
    Date of Patent: November 16, 1993
    Assignee: Bull Information Systems Inc.
    Inventors: Russell W. Guenthner, Clinton B. Eckard, Leonard Rabins, William A. Shelly, Ronald E. Lange, David S. Edwards, Bruce E. Flocken
  • Patent number: 5251321
    Abstract: Binary-Coded-Decimal to binary (DTB) and binary to Binary Coded Decimal (BTD) instructions are executed by an address and execution (AX) chip, a decimal numeric (DN) chip, and a cache. For a DTB instruction, the DN chip receives the operand to be converted from the cache, saves the sign, and stores it in a conversion register. When a bit is converted, a Ready-to-Send signal is sent on a COMFROM bus with a Ready-to-Receive Command on a COMTO bus causes the AX chip to accept the bit and the DN chip to generate the next bit until the resultant operand is produced. If the operand to be converted is negative, the DN chip inverts each remaining bit after the first "1" to obtain a two's-complement result. The result in either case is sent to the cache. For a BTD instruction, the AX chip receives the operand to be converted from the cache, send the sign bit to the DN chip and then the bits of the operand when the Ready-to-Send and Ready to Ready-to-Receive signals are produced.
    Type: Grant
    Filed: September 30, 1992
    Date of Patent: October 5, 1993
    Assignee: Bull HN Information Systems Inc.
    Inventors: Donald C. Boothroyd, Clinton B. Eckard, Ronald E. Lange, William A. Shelly, Ronald W. Yoder
  • Patent number: 5195101
    Abstract: In a Central Processing Unit (CPU) incorporating a Basic Processing Unit (BPU) which includes an address and execution (AX) unit, a decimal numeric (DN) unit and a floating point (FP) unit and also incorporating a cache unit situated logically intermediate the BPU and system memory, BPU data manipulation errors are sensed by duplicating each of the AX, DN and FP chips (i.e., duplicating the BPU) and performing all BPU data manipulation operations redundantly. The outputs from the duplicate BPUs are placed on respective master (MRB) and slave (SRB) result busses which are coupled to the cache unit, and the results are compared, byte-by-byte in the cache unit. If the results are not identical in each byte of the result, the individual chip handling the byte in the cache unit and detecting the no-compare condition issues an individual error signal, and appropriate steps to remedy or otherwise respond to the error signal may be undertaken within the cache unit, within the CPU and within the system.
    Type: Grant
    Filed: June 28, 1990
    Date of Patent: March 16, 1993
    Assignee: Bull HN Information Systems Inc.
    Inventors: Russell W. Guenthner, Bruce E. Flocken, Ronald E. Lange
  • Patent number: 4831622
    Abstract: In a data processing system, there is included a central processing unit (CPU) and a main memory for storing computer words, the CPU including a cache unit. In operation, the CPU requests that a computer word be fetched, the computer word to be fetched being identified by a real address location corresponding to a location where the predetermined computer word is stored in main memory. The CPU request to fetch the computer word is coupled through the cache unit such that the cache unit determines whether the computer word is stored within the cache unit. The cache unit comprises a cache for storing predetermined ones of the compter words. A directory is included for storing partial real address information to a corresponding computer word stored in the cache. A detecting element, operatively connected to the cache and to the directory, determines when a hit occurs without any errors.
    Type: Grant
    Filed: December 22, 1987
    Date of Patent: May 16, 1989
    Assignee: Honeywell Bull Inc.
    Inventors: Marion G. Porter, Marvin K. Webster, Ronald E. Lange
  • Patent number: 4424576
    Abstract: Apparatus for entering encoded data, command, and address information via a keyboard for transfer to an automated maintenance system designed to perform certain tests on or cause selected events in a unit of a data processing system such as the central processing unit. The data, command and address information entered via the keyboard by an operator serves to control the tests performed by or the events caused by the automated maintenance system. The maintenance panel also includes a plurality of display devices for displaying the data, command and address information sent to the automated maintenance system as well as data received by the automated maintenance system from the unit under test indicating the correctness of its performance. In the preferred embodiment, several LED indicators are also used for prompting and status indication.
    Type: Grant
    Filed: September 17, 1979
    Date of Patent: January 3, 1984
    Assignee: Honeywell Information Systems Inc.
    Inventors: Ronald E. Lange, Robert J. Koegel
  • Patent number: 4405978
    Abstract: An apparatus for conducting input output operations with another data processing device in a flexible and low cost manner is comprised of a programmed microprocessor coupled to a keyboard, a parallel port, and a modem. The microprocessor is programmed to periodically scan the keyboard to determine what keys if any are depressed. It also scans the parallel port for incoming data and senses incoming data from the modem by sensing a start bit. Control characters from the keyboard can set options such that incoming data from an input can be simultaneously sent out from the modem and/or parallel port.
    Type: Grant
    Filed: June 25, 1979
    Date of Patent: September 20, 1983
    Assignee: Honeywell Information Systems Inc.
    Inventors: Ronald E. Lange, Steve E. King
  • Patent number: 4363108
    Abstract: There is disclosed herein an apparatus for displaying data and communicating with another data processing device via a parallel port or over a long distance communications network via a full duplex modem, said computer terminal utilizing a microprocessor for programmed control of the terminal. The terminal is capable of displaying information on a standard black and white television set and utilizes a keyboard for entering information to be displayed or sent to the main data processing system. Limited graphics with sixty four graphics patterns are also available by using the microprocessor chip to scan the keyboard and communicate with the modem and parallel ports, and by utilizing a standard television set instead of a cathode ray tube, substantial material cost savings can be made in building the terminal which could be built for under $250 in parts in 1979.
    Type: Grant
    Filed: June 25, 1979
    Date of Patent: December 7, 1982
    Assignee: Honeywell Information Systems Inc.
    Inventors: Ronald E. Lange, Steve E. King
  • Patent number: 4334289
    Abstract: There is disclosed herein an apparatus for encoding, storing, updating and decoding data indicating the order of usage of memory locations as in a cache memory. An array of memory bits is encoded by a field programmable logic array each time a memory device or other peripheral is accessed by a method which need change only a portion of all the memory bits in a row. Each row corresponds to a group of memory locations or peripherals to be monitored. When the order of usage of a group of monitored locations is to be determined a field programmable logic array decodes the corresponding row and outputs a signal indicating the least recently used one of the memory locations of interest.
    Type: Grant
    Filed: February 25, 1980
    Date of Patent: June 8, 1982
    Assignee: Honeywell Information Systems Inc.
    Inventors: Ronald E. Lange, Richard J. Fisher