Abstract: An apparatus is disclosed herein for providing faster memory access for a CPU by utilizing a least recently used scheme for selecting a storage location in which to store data retrieved from main memory upon a cache miss. A duplicate directory arrangement is also disclosed for selective clearing of the cache in multiprocessor systems where data in a cache becomes obsolete by virtue of a change made to the corresponding data in main memory by another processor. The advantage of higher overall speed for CPU operations is achieved because of the higher hit ratio provided by the disclosed arrangement. In the preferred embodiment, the cache utilizes: a cache store for storing data; primary and duplicate directories for identifying the data stored in the cache; a full/empty array to mark the status of the storage locations; a least recently used array to indicate where incoming data should be stored; and a control means to orchestrate all these elements.

Abstract: There is disclosed herein an apparatus for use in automated testing of elements in data processing systems such as the central processing unit. The system is comprised of a microprocessor with associated firmware, RAM and peripheral communications devices. There are two communication interface ports for receiving commands and instructions from local and remote computer terminals or from data processing units programmed to cause the testing apparatus to perform predetermined sequences of tests. There is also a port for connection to a portable maintenance panel which can be held in the hand of a field engineer for controlling the testing apparatus. The system is designed to replace prior art maintenance panels used for debugging computer hardware.

Abstract: Apparatus for use in coupling an automated maintenance system of general utility to a central processing unit of a data processing system. The interface apparatus is comprised of path control and operational condition control registers to control and enable the paths accessed by the automated maintenance system and to control the conditions of operation of the central processing unit. A control point register stores control point information from the central processing unit indicating its internal status. This information is read and displayed by the automated maintenance system. Address and data registers serve to buffer data and addresses exchanged between the automated maintenance system and the CPU. The disclosed interface apparatus allows a general utility automated maintenance system to be adapted to test a specific central processing unit.