Patents by Inventor Ronald E. Reedy

Ronald E. Reedy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10351267
    Abstract: A satellite system operates at altitudes between 100 and 350 km relying on vehicles including a self-sustaining ion engine to counteract atmospheric drag to maintain near-constant orbit dynamics. The system operates at altitudes that are substantially lower than traditional satellites, reducing size, weight and cost of the vehicles and their constituent subsystems such as optical imagers, radars, and radio links. The system can include a large number of lower cost, mass, and altitude vehicles, enabling revisit times substantially shorter than previous satellite systems. The vehicles spend their orbit at low altitude, high atmospheric density conditions that have heretofore been virtually impossible to consider for stable orbits. Short revisit times at low altitudes enable near-real time imaging at high resolution and low cost. At such altitudes, the system has no impact on space junk issues of traditional LEO orbits, and is self-cleaning in that space junk or disabled craft will de-orbit.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: July 16, 2019
    Assignee: Skeyeon, Inc.
    Inventors: Ronald E. Reedy, Thomas E. Schwartzentruber
  • Publication number: 20190016672
    Abstract: A satellite system operates at altitudes between 180 km and 350 km relying on vehicles including an engine to counteract atmospheric drag to maintain near-constant orbit dynamics. The system operates at altitudes that are substantially lower than traditional satellites, reducing size, weight and cost of the vehicles and their constituent subsystems such as optical imagers, radars, and radio links. The system can include a large number of lower cost, mass, and altitude vehicles, enabling revisit times substantially shorter than previous satellite systems. The vehicles spend their orbit at low altitude, high atmospheric density conditions that have heretofore been virtually impossible to consider for stable orbits. Short revisit times at low altitudes enable near-real time imaging at high resolution and low cost. At such altitudes, the system has no impact on space junk issues of traditional LEO orbits, and is self-cleaning in that space junk or disabled craft will de-orbit.
    Type: Application
    Filed: September 12, 2018
    Publication date: January 17, 2019
    Inventors: Ronald E. Reedy, Thomas E. Schwartzentruber
  • Publication number: 20180155067
    Abstract: A satellite system operates at altitudes between 100 and 350 km relying on vehicles including a self-sustaining ion engine to counteract atmospheric drag to maintain near-constant orbit dynamics. The system operates at altitudes that are substantially lower than traditional satellites, reducing size, weight and cost of the vehicles and their constituent subsystems such as optical imagers, radars, and radio links. The system can include a large number of lower cost, mass, and altitude vehicles, enabling revisit times substantially shorter than previous satellite systems. The vehicles spend their orbit at low altitude, high atmospheric density conditions that have heretofore been virtually impossible to consider for stable orbits. Short revisit times at low altitudes enable near-real time imaging at high resolution and low cost. At such altitudes, the system has no impact on space junk issues of traditional LEO orbits, and is self-cleaning in that space junk or disabled craft will de-orbit.
    Type: Application
    Filed: February 22, 2017
    Publication date: June 7, 2018
    Inventors: Ronald E. Reedy, Thomas E. Schwartzentruber
  • Publication number: 20180156924
    Abstract: A satellite system operates at altitudes between 180 km and 350 km relying on vehicles including an engine to counteract atmospheric drag to maintain near-constant orbit dynamics. The system operates at altitudes that are substantially lower than traditional satellites, reducing size, weight and cost of the vehicles and their constituent subsystems such as optical imagers, radars, and radio links. The system can include a large number of lower cost, mass, and altitude vehicles, enabling revisit times substantially shorter than previous satellite systems. The vehicles spend their orbit at low altitude, high atmospheric density conditions that have heretofore been virtually impossible to consider for stable orbits. Short revisit times at low altitudes enable near-real time imaging at high resolution and low cost. At such altitudes, the system has no impact on space junk issues of traditional LEO orbits, and is self-cleaning in that space junk or disabled craft will de-orbit.
    Type: Application
    Filed: January 11, 2018
    Publication date: June 7, 2018
    Inventors: Ronald E. Reedy, Thomas E. Schwartzentruber
  • Publication number: 20180159617
    Abstract: A satellite system operates at altitudes between 100 and 350 km relying on vehicles including a self-sustaining ion engine to counteract atmospheric drag to maintain near-constant orbit dynamics. The system operates at altitudes that are substantially lower than traditional satellites, reducing size, weight and cost of the vehicles and their constituent subsystems such as optical imagers, radars, and radio links. The system can include a large number of lower cost, mass, and altitude vehicles, enabling revisit times substantially shorter than previous satellite systems. The vehicles spend their orbit at low altitude, high atmospheric density conditions that have heretofore been virtually impossible to consider for stable orbits. Short revisit times at low altitudes enable near-real time imaging at high resolution and low cost. At such altitudes, the system has no impact on space junk issues of traditional LEO orbits, and is self-cleaning in that space junk or disabled craft will de-orbit.
    Type: Application
    Filed: January 11, 2018
    Publication date: June 7, 2018
    Inventors: Dan Nobbe, Ronald E. Reedy
  • Patent number: 6910812
    Abstract: An integrated circuit/optoelectronic packaging system (100) which comprises OE and IC components packaged to provide electrical input/output, thermal management, an optical window, and precise passive or mechanical alignment to external optical receivers or transmitters. A transparent insulating substrate having electrical circuitry in a thin silicon layer formed on its top side is positioned between the optical fiber and the optoelectronic device such that an optical path is described between the optoelectronic device and the optical fiber core through the transparent insulating substrate. The optoelectronic devices are mounted on the transparent insulating substrate in a precise positional relationship to guide holes in the substrate. The optical fibers are fixed in an optical fiber connector and are held in a precise positional relationship to guide holes in the connector.
    Type: Grant
    Filed: May 15, 2002
    Date of Patent: June 28, 2005
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Richard Pommer, Charles B. Kuznia, Tri Q. Le, Richard T. Hagen, Ronald E. Reedy, James S. Cable, Donald J. Albares, Mark Miscione
  • Patent number: 6869229
    Abstract: An optical-optoelectronic coupling structure comprising a flip-chip optoelectronic/ultrathin silicon-on-sapphire device mounted on a V-groove, optical-fiber-bearing carrier substrate, including light-reflective structures for launching light into the optical fiber core or transmitting light emitted by the optical fiber core to the optoelectronic device. The optical fiber may be immobilized in the V-groove using a curable resin adhesive characterized by a refractive index substantially similar to the refractive index of the optical fiber.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: March 22, 2005
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Ronald E. Reedy, James S. Cable, Charles B. Kuznia, Donald J. Albares, Tri Q. Le
  • Patent number: 6690056
    Abstract: A non-volatile storage cell manufactured in a standard CMOS process in silicon on insulator is described. The cell is manufactured in a standard single polysilicon layer CMOS process applied to silicon on insulator starting substrates. Two versions of the cell are described with distinct mechanisms for writing onto a floating polysilicon layer storage node. The basic cell comprises crossed N- and P- transistors which share a common channel region and a common floating gate over the channel. Current in the channel results in charge injection through the gate oxide and onto the polysilicon gate conductor where it is permanently stored. Since both N and P type transistors are available, charge of both polarities can be injected. Application of a voltage to either of the transistors results in a current or voltage which is used to perform the reading function. Multiple variations of the cell and its operation are also described along with unique applications of the cell.
    Type: Grant
    Filed: October 19, 1999
    Date of Patent: February 10, 2004
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Ronald E. Reedy, James S. Cable
  • Patent number: 6667506
    Abstract: Multiple variations of a variable capacitor or varactor 10 with built-in programmability; exhibiting high quality, Q, factors; manufactured in a standard CMOS process in silicon on insulator. The cell 10 is manufactured in a standard single polysilicon layer CMOS process applied to silicon on insulator 30 starting substrates. The variable capacitor cell 10 combined with a non-volatile mechanism for programming the tuning range of the varactor 10 results in a varactor 10 which can be tuned and adjusted in an on-chip and purely electronic fashion. The basic variable capacitor cell 10 comprises a floating gate MOS variable capacitor, CMOS, in series with a metal to floating gate fixed capacitor CM/FG.
    Type: Grant
    Filed: March 25, 2000
    Date of Patent: December 23, 2003
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Ronald E. Reedy, James S. Cable
  • Publication number: 20030201462
    Abstract: An integrated circuit/optoelectronic packaging system (100) which comprises OE and IC components packaged to provide electrical input/output, thermal management, an optical window, and precise passive or mechanical alignment to external optical receivers or transmitters. A transparent insulating substrate having electrical circuitry in a thin silicon layer formed on its top side is positioned between the optical fiber and the optoelectronic device such that an optical path is described between the optoelectronic device and the optical fiber core through the transparent insulating substrate. Arrays of fibers may be coupled to arrays of optoelectronic devices through a single transparent substrate. The optoelectronic devices are mounted on the transparent insulating substrate in a precise positional relationship to guide holes in the substrate. The optical fibers are fixed in an optical fiber connector and are held in a precise positional relationship to guide holes in the connector.
    Type: Application
    Filed: May 15, 2002
    Publication date: October 30, 2003
    Inventors: Richard Pommer, Charles B. Kuznia, Tri Q. Le, Richard T. Hagen, Ronald E. Reedy, James S. Cable, Donald J. Albares, Mark Miscione
  • Patent number: 6583445
    Abstract: An integrated electronic-optoelectronic module comprising: an ultrathin silicon-on-sapphire composite substrate; at least one electronic device fabricated in the ultrathin silicon; and at least one optoelectronic device bonded to the ultrathin silicon-on-sapphire composite substrate and in electrical communication with the at least one electronic device fabricated in the ultrathin silicon layer. For example, VCSELs and photodetectors are integrated with CMOS electronic circuitry to provide useful modules for electro-optical interconnects for computing and switching systems.
    Type: Grant
    Filed: September 8, 2000
    Date of Patent: June 24, 2003
    Assignees: Peregrine Semiconductor Corporation, George Mason University, John Hopkins University, The United States of America as represented by the Secretary of the Army
    Inventors: Ronald E. Reedy, Ravindra A. Athale, George J. Simonis, Andreas G. Andreou, Alyssa Apsel, Zaven Kalayjian, Philippe O. Pouliquen
  • Publication number: 20020131727
    Abstract: An optical-optoelectronic coupling structure comprising a flip-chip optoelectronic/ultrathin silicon-on-sapphire device mounted on a V-groove, optical-fiber-bearing carrier substrate, including light-reflective structures for launching light into the optical fiber core or transmitting light emitted by the optical fiber core to the optoelectronic device. The optical fiber may be immobilized in the V-groove using a curable resin adhesive characterized by a refractive index substantially similar to the refractive index of the optical fiber.
    Type: Application
    Filed: March 15, 2002
    Publication date: September 19, 2002
    Inventors: Ronald E. Reedy, James S. Cable, Charles B. Kuznia, Donald J. Albares, Tri Q. Le
  • Patent number: 6090648
    Abstract: A method of making a self-aligned, integrated resistor load on ultrathin silicon on sapphire film, with the method being used to manufacture an FET and a resistor load. While the film can be used, for example, to manufacture a four transistor SRAM, it is not limited to such applications. The method encompasses an integral resistor load which can be integrated with analog components or formed as part of an integrated circuit for electrostatic discharge (ESD) circuitry, or the like. The resistor load can be integrally formed from the same silicon island which forms a corresponding transistor. Because the resistor load can be made from, and integral with, the ultra thin silicon material, it can be automatically self-aligned to the transistor. The self-aligned, integrated resistor loads are comprised of an insulating substrate, with a layer of silicon formed on the insulating substrate.
    Type: Grant
    Filed: August 31, 1998
    Date of Patent: July 18, 2000
    Assignee: Peregrine Semiconductor Corp.
    Inventors: Ronald E. Reedy, Mark L. Burgener
  • Patent number: 6057555
    Abstract: A high-frequency wireless communication system on a single ultrathin silicon on sapphire chip is presented. This system incorporates analog, digital (logic and memory) and high radio frequency circuits on a single ultrathin silicon on sapphire chip. The devices are fabricated using conventional bulk silicon CMOS processing techniques. Advantages include single chip architecture, superior high frequency performance, low power consumption and cost effective fabrication.
    Type: Grant
    Filed: October 26, 1998
    Date of Patent: May 2, 2000
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Ronald E. Reedy, Mark L. Burgener
  • Patent number: 5973382
    Abstract: An integrated circuit is provided which comprises: an insulating substrate; a semiconductor layer formed on the insulating substrate; a MOSFET including a source, drain and channel formed in the silicon layer and a gate adjacent to the channel; a gate terminal; and a conductor interconnecting the source and drain so as to maintain them at a common potential.
    Type: Grant
    Filed: May 23, 1997
    Date of Patent: October 26, 1999
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Mark L. Burgener, Ronald E. Reedy, John Y. Sung
  • Patent number: 5973363
    Abstract: An integrated circuit comprising an insulating substrate; a layer of silicon formed on said insulating substrate; a p-channel transistor and an n-channel transistor formed in said silicon layer and interconnected in a CMOS circuit; wherein the ratio of transistor p-channel length to transistor n-channel length in the CMOS circuit is less than or equal to one.
    Type: Grant
    Filed: March 9, 1995
    Date of Patent: October 26, 1999
    Assignee: Peregrine Semiconductor Corp.
    Inventors: David R. Staab, Richard M. Greene, Mark L. Burgener, Ronald E. Reedy
  • Patent number: 5930638
    Abstract: A diffused resistor and a method for making the diffused resistor are disclosed. The diffused resistor is formed in a substantially pure portion of the thin semiconductor layer that is formed on an insulating substrate. The thin semiconductor layer has low a number of defects and mid-band gap states. This portion may be located in an electrically isolated region of the thin semiconductor layer. A resistive region is used to provide the resistance of the diff-used resistor. Contact regions are provided continguous with the the resistive region. The diff-used resistor can be formed by themselves or in conjunction with other circuit elements, such as a MOSFET, for example. Accordingly, also disclosed is a method for making the diffused resitor in conjunction with a MOSFET. The diffused resistor and the MOSFET are formed in electrically isolated semiconductor islands. The electrically isolated semiconductor islands are formed from the high quality thin semiconductor layer.
    Type: Grant
    Filed: August 19, 1997
    Date of Patent: July 27, 1999
    Assignee: Peregrine Semiconductor Corp.
    Inventors: Ronald E. Reedy, Mark L. Burgener
  • Patent number: 5895957
    Abstract: A process is disclosed for preparing a silicon-on-sapphire wafer suited for fabrication of fully depleted field effect transistors. A fully depleted field effect transistor (FET) which has minimum parasitic charge in the conduction channel and a process to make same are described. The device is made in and relies on the silicon layer on sapphire which has minimal charge intentionally introduced into the conduction channel. Both N-type and P-type transistors are described. Methods for defining threshold voltage are also described. Specific examples of the devices are presented including specific materials selections for threshold voltage options.Manufacturing processes are described, including a preferred embodiment based on ultra thin silicon on sapphire. The devices can be fabricated using conventional silicon techniques; both silicided and non-silicided versions are presented.
    Type: Grant
    Filed: January 3, 1997
    Date of Patent: April 20, 1999
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Ronald E. Reedy, Mark L. Burgener
  • Patent number: 5883396
    Abstract: A high-frequency wireless communication system on a single ultrathin silicon on sapphire chip is presented. This system incorporates analog, digital (logic and memory) and high radio frequency circuits on a single ultrathin silicon on sapphire chip. The devices are fabricated using conventional bulk silicon CMOS processing techniques. Advantages include single chip architecture, superior high frequency performance, low power consumption and cost effective fabrication.
    Type: Grant
    Filed: October 17, 1996
    Date of Patent: March 16, 1999
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Ronald E. Reedy, Mark L. Burgener
  • Patent number: 5864162
    Abstract: A thin silicon layer transistor integrated with a resistor. The resistor is self-aligned and contiguous with the transistor and is also formed of the same thin silicon layer as the transistor. This structure is particularly suitable for an SRAM circuit in order to simplify processing steps and to conserve area on SOS designs.
    Type: Grant
    Filed: December 13, 1996
    Date of Patent: January 26, 1999
    Assignee: Peregrine Seimconductor Corporation
    Inventors: Ronald E. Reedy, Mark L. Burgener