Abstract: An optical-optoelectronic coupling structure comprising a flip-chip optoelectronic/ultrathin silicon-on-sapphire device mounted on a V-groove, optical-fiber-bearing carrier substrate, including light-reflective structures for launching light into the optical fiber core or transmitting light emitted by the optical fiber core to the optoelectronic device. The optical fiber may be immobilized in the V-groove using a curable resin adhesive characterized by a refractive index substantially similar to the refractive index of the optical fiber.

Abstract: A non-volatile storage cell manufactured in a standard CMOS process in silicon on insulator is described. The cell is manufactured in a standard single polysilicon layer CMOS process applied to silicon on insulator starting substrates. Two versions of the cell are described with distinct mechanisms for writing onto a floating polysilicon layer storage node. The basic cell comprises crossed N- and P- transistors which share a common channel region and a common floating gate over the channel. Current in the channel results in charge injection through the gate oxide and onto the polysilicon gate conductor where it is permanently stored. Since both N and P type transistors are available, charge of both polarities can be injected. Application of a voltage to either of the transistors results in a current or voltage which is used to perform the reading function. Multiple variations of the cell and its operation are also described along with unique applications of the cell.

Abstract: Multiple variations of a variable capacitor or varactor 10 with built-in programmability; exhibiting high quality, Q, factors; manufactured in a standard CMOS process in silicon on insulator. The cell 10 is manufactured in a standard single polysilicon layer CMOS process applied to silicon on insulator 30 starting substrates. The variable capacitor cell 10 combined with a non-volatile mechanism for programming the tuning range of the varactor 10 results in a varactor 10 which can be tuned and adjusted in an on-chip and purely electronic fashion. The basic variable capacitor cell 10 comprises a floating gate MOS variable capacitor, CMOS, in series with a metal to floating gate fixed capacitor CM/FG.

Abstract: An integrated circuit/optoelectronic packaging system (100) which comprises OE and IC components packaged to provide electrical input/output, thermal management, an optical window, and precise passive or mechanical alignment to external optical receivers or transmitters. A transparent insulating substrate having electrical circuitry in a thin silicon layer formed on its top side is positioned between the optical fiber and the optoelectronic device such that an optical path is described between the optoelectronic device and the optical fiber core through the transparent insulating substrate. Arrays of fibers may be coupled to arrays of optoelectronic devices through a single transparent substrate. The optoelectronic devices are mounted on the transparent insulating substrate in a precise positional relationship to guide holes in the substrate. The optical fibers are fixed in an optical fiber connector and are held in a precise positional relationship to guide holes in the connector.

Abstract: An integrated electronic-optoelectronic module comprising: an ultrathin silicon-on-sapphire composite substrate; at least one electronic device fabricated in the ultrathin silicon; and at least one optoelectronic device bonded to the ultrathin silicon-on-sapphire composite substrate and in electrical communication with the at least one electronic device fabricated in the ultrathin silicon layer. For example, VCSELs and photodetectors are integrated with CMOS electronic circuitry to provide useful modules for electro-optical interconnects for computing and switching systems.

Abstract: An optical-optoelectronic coupling structure comprising a flip-chip optoelectronic/ultrathin silicon-on-sapphire device mounted on a V-groove, optical-fiber-bearing carrier substrate, including light-reflective structures for launching light into the optical fiber core or transmitting light emitted by the optical fiber core to the optoelectronic device. The optical fiber may be immobilized in the V-groove using a curable resin adhesive characterized by a refractive index substantially similar to the refractive index of the optical fiber.

Abstract: A method of making a self-aligned, integrated resistor load on ultrathin silicon on sapphire film, with the method being used to manufacture an FET and a resistor load. While the film can be used, for example, to manufacture a four transistor SRAM, it is not limited to such applications. The method encompasses an integral resistor load which can be integrated with analog components or formed as part of an integrated circuit for electrostatic discharge (ESD) circuitry, or the like. The resistor load can be integrally formed from the same silicon island which forms a corresponding transistor. Because the resistor load can be made from, and integral with, the ultra thin silicon material, it can be automatically self-aligned to the transistor. The self-aligned, integrated resistor loads are comprised of an insulating substrate, with a layer of silicon formed on the insulating substrate.

Abstract: A high-frequency wireless communication system on a single ultrathin silicon on sapphire chip is presented. This system incorporates analog, digital (logic and memory) and high radio frequency circuits on a single ultrathin silicon on sapphire chip. The devices are fabricated using conventional bulk silicon CMOS processing techniques. Advantages include single chip architecture, superior high frequency performance, low power consumption and cost effective fabrication.

Abstract: An integrated circuit comprising an insulating substrate; a layer of silicon formed on said insulating substrate; a p-channel transistor and an n-channel transistor formed in said silicon layer and interconnected in a CMOS circuit; wherein the ratio of transistor p-channel length to transistor n-channel length in the CMOS circuit is less than or equal to one.

Abstract: An integrated circuit is provided which comprises: an insulating substrate; a semiconductor layer formed on the insulating substrate; a MOSFET including a source, drain and channel formed in the silicon layer and a gate adjacent to the channel; a gate terminal; and a conductor interconnecting the source and drain so as to maintain them at a common potential.

Abstract: A diffused resistor and a method for making the diffused resistor are disclosed. The diffused resistor is formed in a substantially pure portion of the thin semiconductor layer that is formed on an insulating substrate. The thin semiconductor layer has low a number of defects and mid-band gap states. This portion may be located in an electrically isolated region of the thin semiconductor layer. A resistive region is used to provide the resistance of the diff-used resistor. Contact regions are provided continguous with the the resistive region. The diff-used resistor can be formed by themselves or in conjunction with other circuit elements, such as a MOSFET, for example. Accordingly, also disclosed is a method for making the diffused resitor in conjunction with a MOSFET. The diffused resistor and the MOSFET are formed in electrically isolated semiconductor islands. The electrically isolated semiconductor islands are formed from the high quality thin semiconductor layer.

Abstract: A process is disclosed for preparing a silicon-on-sapphire wafer suited for fabrication of fully depleted field effect transistors. A fully depleted field effect transistor (FET) which has minimum parasitic charge in the conduction channel and a process to make same are described. The device is made in and relies on the silicon layer on sapphire which has minimal charge intentionally introduced into the conduction channel. Both N-type and P-type transistors are described. Methods for defining threshold voltage are also described. Specific examples of the devices are presented including specific materials selections for threshold voltage options.Manufacturing processes are described, including a preferred embodiment based on ultra thin silicon on sapphire. The devices can be fabricated using conventional silicon techniques; both silicided and non-silicided versions are presented.

Abstract: A high-frequency wireless communication system on a single ultrathin silicon on sapphire chip is presented. This system incorporates analog, digital (logic and memory) and high radio frequency circuits on a single ultrathin silicon on sapphire chip. The devices are fabricated using conventional bulk silicon CMOS processing techniques. Advantages include single chip architecture, superior high frequency performance, low power consumption and cost effective fabrication.

Abstract: A thin silicon layer transistor integrated with a resistor. The resistor is self-aligned and contiguous with the transistor and is also formed of the same thin silicon layer as the transistor. This structure is particularly suitable for an SRAM circuit in order to simplify processing steps and to conserve area on SOS designs.

Abstract: A high-frequency wireless communication system on a single ultrathin silicon on sapphire chip is presented. This system incorporates analog, digital (logic and memory) and high radio frequency circuits on a single ultrathin silicon on sapphire chip. The devices are fabricated using conventional bulk silicon CMOS processing techniques. Advantages include single chip architecture, superior high frequency performance, low power consumption and cost effective fabrication.

Abstract: A method of simultaneously improving the spectral response and dark current characteristics of an image gathering detector is disclosed. The method uses an excimer laser to redistribute and activate ion implanted dopant species in the backside of an image gathering device such as a backside-illuminated CCD. Alternately, the excimer laser is used to incorporate dopants from a gaseous ambient into the backside of the image gathering device and simultaneously redistribute and activate the dopants. The redistribution of the dopant is controlled by the laser pulses and provides for a peak dopant concentration at the back surface of the image gathering device which provides for improved spectral response and simultaneously improves dark current characteristics.

Abstract: A method uses an excimer laser to activate previously implanted dopant species in the backside of a backside-illuminated CCD or to incorporate dopant ions from a gaseous ambient into the backside of a backside-illuminated CCD and simultaneously activate. The controlled ion implantation of the backside and subsequent thin layer heating by the short wavelength pulsed excimer laser energy activates the dopant and provides for an improved dark current response and improved spectral response. The energy of the pulsed excimer laser is applied uniformly across a backside-illuminated CCD in a very thin layer of the semiconductor substrate (usually silicon) material that requires annealing to uniformly activate the dopant. The very thin layer of the material can be heated to exceedingly high temperatures on a nanosecond time scale while the bulk of the delicate CCD substrate remains at low temperature.

Abstract: A high-frequency wireless communication system on a single ultrathin silicon on sapphire chip is presented. This system incorporates analog, digital (logic and memory) and high radio frequency circuits on a single ultrathin silicon on sapphire chip. The devices are fabricated using conventional bulk silicon CMOS processing techniques. Advantages include single chip architecture, superior high frequency performance, low power consumption and cost effective fabrication.

Abstract: A process is disclosed for preparing a silicon-on-sapphire wafer suited for fabrication of fully depleted field effect transistors. A fully depleted field effect transistor (FET) which has minimum parasitic charge in the conduction channel and a process to make same are described. The device is made in and relies on the silicon layer on sapphire which has minimal charge intentionally introduced into the conduction channel. Both N-type and P-type transistors are described. Methods for defining threshold voltage are also described. Specific examples of the devices are presented including specific materials selections for threshold voltage options.Manufacturing processes are described, including a preferred embodiment based on ultra thin silicon on sapphire. The devices can be fabricated using conventional silicon techniques; both silicided and non-silicided versions are presented.

Abstract: A high-frequency wireless communication system on a single ultrathin silicon on sapphire chip is presented. This system incorporates analog, digital (logic and memory) and high radio frequency circuits on a single ultrathin silicon on sapphire chip. The devices are fabricated using conventional bulk silicon CMOS processing techniques. Advantages include single chip architecture, superior high frequency performance, low power consumption and cost effective fabrication.