Patents by Inventor Ronald Eisele

Ronald Eisele has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11776932
    Abstract: Process for producing an electronic subassembly by low-temperature pressure sintering, comprising the following steps: arranging an electronic component on a circuit carrier having a conductor track, connecting the electronic component to the circuit carrier by the low-temperature pressure sintering of a joining material which connects the electronic component to the circuit carrier, characterized in that, to avoid the oxidation of the electronic component or of the conductor track, the low-temperature pressure sintering is carried out in a low-oxygen atmosphere having a relative oxygen content of 0.005 to 0.3%.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: October 3, 2023
    Assignee: Danfoss Silicon Power GmbH
    Inventors: Ronald Eisele, Holger Ulrich
  • Patent number: 11626383
    Abstract: Process for producing an electronic subassembly by low-temperature pressure sintering, comprising the following steps: arranging an electronic component on a circuit carrier having a conductor track, connecting the electronic component to the circuit carrier by the low-temperature pressure sintering of a joining material which connects the electronic component to the circuit carrier, characterized in that, to avoid the oxidation of the electronic component or of the conductor track, the low-temperature pressure sintering is carried out in a low-oxygen atmosphere having a relative oxygen content of 0.005 to 0.3%.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: April 11, 2023
    Assignee: Danfoss Silicon Power GmbH
    Inventors: Ronald Eisele, Holger Ulrich
  • Publication number: 20220302072
    Abstract: Semiconductor module including a semiconductor and including a shaped metal body that is electrically contacted by the semiconductor, for forming a contact surface for an electrical conductor, wherein the shaped metal body is bent or folded. A method is also described for establishing electrical contacting of an electrical conductor on a semiconductor, said method including the steps of: fastening a bent or folded shaped metal body of a constant thickness to the semiconductor by means of a first fastening method and then fastening the electrical conductor to the shaped metal body by means of a second fastening method.
    Type: Application
    Filed: April 30, 2020
    Publication date: September 22, 2022
    Inventors: André Bastos Abibe, Frank Osterwald, Jacek Rudzki, Martin Becker, Ronald Eisele, David Benning
  • Publication number: 20220302073
    Abstract: Semiconductor module having a first substrate, a second substrate and a spacer distancing the substrates from each other, wherein the spacer is formed by at least one elastic shaped metal body.
    Type: Application
    Filed: May 6, 2020
    Publication date: September 22, 2022
    Inventors: Martin Becker, André Bastos Abibe, Ronald Eisele, Jacek Rudzki, Frank Osterwald, David Benning
  • Publication number: 20220293489
    Abstract: The invention relates to a power electronics module including a first circuit carrier (5,10, 11), as well as an electronic assembly (20, 30) arranged in an electrically contacting manner on the upper flat side of the first circuit carrier (5, 10, 11), and a first cooling element (40) in thermal contact with the underside of the first circuit carrier (5, 10, 11), wherein the module has at least one second assembly (20, 30) arranged on the upper side of a second circuit carrier (5, 10, 11) and a second cooling element (40) arranged on the underside of the second circuit carrier (5, 10, 11), wherein the first and the second circuit carriers (5, 10, 11) are arranged with their upper sides facing one another and at least one central heat sink (60, 61, 63, 64) that is electrically insulated from the assemblies (20, 30) is arranged in the space between the assemblies (20, 30), wherein the assemblies (20, 30) and the at least one central heat sink (60, 61, 63, 64) are embedded in a heat-conducting potting compound (5
    Type: Application
    Filed: April 30, 2020
    Publication date: September 15, 2022
    Inventors: Stefan Behrendt, Ronald Eisele
  • Publication number: 20220295662
    Abstract: The invention relates to a power electronics module including a flat circuit carrier (5) and an electronic assembly (10) arranged in an electrically contacting manner on the upper flat side of the circuit carrier (5) and cooling bodies (20) thermally in contact with the underside of the circuit carrier (5), wherein a heat-conducting bridge (30) arranged on the upper side of the circuit carrier (5), spanning the assembly (10) and extensively covering same, wherein the heat-conducting bridge (30) is in thermal contact with the cooling body (20) at mounting points arranged next to the assembly (10) and the space between the heat-conducting bridge (30) and the circuit carrier (5) is filled with a heat-conducting potting compound (50).
    Type: Application
    Filed: April 30, 2020
    Publication date: September 15, 2022
    Inventors: Stefan Behrendt, Ronald Eisele
  • Patent number: 11400514
    Abstract: Sintering tool (10) with a cradle for receiving an electronic subassembly (BG) to be sintered, characterized by at least one support bracket (20), arranged at two locations opposite the cradle, for fixing a protective film (30) covering the electronic subassembly (BG).
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: August 2, 2022
    Assignee: Danfoss Silicon Power GmbH
    Inventors: Frank Osterwald, Martin Becker, Lars Paulsen, Jacek Rudzki, Holger Ulrich, Ronald Eisele
  • Publication number: 20210210403
    Abstract: One aspect relates to a heat spreading plate having at least one cooling fin. The heat spreading plate includes at least a first layer and at least a second layer, and at least one surface portion bent out of a base surface of the second layer forms a cooling fin.
    Type: Application
    Filed: February 9, 2017
    Publication date: July 8, 2021
    Applicant: Heraeus Deutschland GmbH & CO., KG
    Inventor: Ronald EISELE
  • Publication number: 20210210416
    Abstract: One aspect relates to a method for producing a substrate plate for a large-area semiconductor element, particularly for a thyristor wafer or a diode. At least one first layer made from a first material, with a first coefficient of expansion, and at least one second layer made from a second material of low expandability, with a second coefficient of expansion, which is smaller than the first coefficient of expansion, are bonded to one another by means of a low-temperature sintering method at a bonding temperature of 150° C.-300° C. At least one first bonding layer made from a bonding material is formed between the first layer and the second layer and the bonding temperature substantially corresponds to the mounting temperature during the bonding of the substrate plate produced with at least one large-area semiconductor element.
    Type: Application
    Filed: February 9, 2017
    Publication date: July 8, 2021
    Applicant: Heraeus Deutschland GmbH & Co. KG
    Inventor: Ronald EISELE
  • Publication number: 20210210406
    Abstract: One aspect relates to a method for producing a circuit carrier for a semiconductor component. At least one first copper layer or one first copper-alloy layer with a first coefficient of expansion and at least one second layer made from a second material of low expandability with a second coefficient of expansion, which is smaller than the first coefficient of expansion, are bonded to one another by means of a low-temperature sintering method at a bonding temperature of 150° C. to 300° C.
    Type: Application
    Filed: February 8, 2017
    Publication date: July 8, 2021
    Applicant: Heraeus deutschland GmbH & Co. KG
    Inventor: Ronald EISELE
  • Publication number: 20210202350
    Abstract: One aspect relates to a method for producing a heat-spreading plate for a circuit carrier. At least one first layer made of a first material having a first coefficient of expansion and at least one second layer made of a second, low-stretch material having a second coefficient of expansion that is smaller than the first coefficient of expansion are bonded to each other at a bonding temperature of 150° C.-300° C. by means of a low-temperature sintering process. At least one bonding layer from a bonding material is formed between the first layer and the second layer and the bonding temperature essentially corresponding to the mounting temperature at which the produced heat spreading plate is connected to at least one circuit carrier.
    Type: Application
    Filed: February 9, 2017
    Publication date: July 1, 2021
    Applicant: Heraeus Deutschland GmbH & Co. KG
    Inventor: Ronald EISELE
  • Publication number: 20210104488
    Abstract: Process for producing an electronic subassembly by low-temperature pressure sintering, comprising the following steps: arranging an electronic component on a circuit carrier having a conductor track, connecting the electronic component to the circuit carrier by the low-temperature pressure sintering of a joining material which connects the electronic component to the circuit carrier, characterized in that, to avoid the oxidation of the electronic component or of the conductor track, the low-temperature pressure sintering is carried out in a low-oxygen atmosphere having a relative oxygen content of 0.005 to 0.3%.
    Type: Application
    Filed: December 18, 2020
    Publication date: April 8, 2021
    Inventors: Ronald Eisele, Holger Ulrich
  • Publication number: 20210016353
    Abstract: Sintering tool (10) with a cradle for receiving an electronic subassembly (BG) to be sintered, characterized by at least one support bracket (20), arranged at two locations opposite the cradle, for fixing a protective film (30) covering the electronic subassembly (BG).
    Type: Application
    Filed: October 1, 2020
    Publication date: January 21, 2021
    Inventors: Frank Osterwald, Martin Becker, Lars Paulsen, Jacek Rudzki, Holger Ulrich, Ronald Eisele
  • Patent number: 10832995
    Abstract: A power module (10) having a leadframe (20), a power semiconductor (30) arranged on the leadframe (20), a base plate (40) for dispersing heat generated by the power semiconductor (30) and a potting compound (50) surrounding the leadframe (20) and the power semiconductor (30), that physically connects the power semiconductor (30) and/or the leadframe (20) to the base plate(40).
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: November 10, 2020
    Assignee: Danfoss Silicon Power GmbH
    Inventors: Ronald Eisele, Frank Osterwald
  • Patent number: 10818633
    Abstract: Tool (10) for the lower die of a sintering device, the tool (10) having a rest (20) for an electronic subassembly (30) comprising a circuit carrier, to be sintered, where the rest (20) is formed from a material with a coefficient of linear expansion that is close to the coefficient of expansion of the circuit carrier of the electronic subassembly (30).
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: October 27, 2020
    Assignee: Danfoss Silicon Power GmbH
    Inventors: Frank Osterwald, Ronald Eisele, Martin Becker, Jacek Rudzki, Lars Paulsen, Holger Ulrich
  • Patent number: 10814396
    Abstract: Sintering tool (10) with a cradle for receiving an electronic subassembly (BG) to be sintered, characterized by at least one support bracket (20), arranged at two locations opposite the cradle, for fixing a protective film (30) covering the electronic subassembly (BG).
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: October 27, 2020
    Assignee: Danfoss Silicon Power GmbH
    Inventors: Frank Osterwald, Martin Becker, Lars Paulsen, Jacek Rudzki, Holger Ulrich, Ronald Eisele
  • Patent number: 10685894
    Abstract: A semi-conductor module with an encapsulating mass that covers a semi-conductor component, in which the encapsulating mass is cement.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: June 16, 2020
    Assignee: Heraeus Deutschland GmbH & Co. KG
    Inventor: Ronald Eisele
  • Patent number: 10607962
    Abstract: A method for manufacturing semiconductor chips (2, 3) having arranged thereon metallic shaped bodies (6), having the following steps: arranging a plurality of metallic shaped bodies (6) on a processed semiconductor wafer while forming a layer arranged between the semiconductor wafer and the metallic shaped bodies (6), exhibiting a first connection material (4) and a second connection material (5), and processing the first connection material (4) for connecting the metallic shaped bodies (6) to the semiconductor wafer without processing the second connecting material (5), wherein the semiconductor chips (2, 3) are separated either prior to arranging the metallic shaped bodies (6) on the semiconductor wafer or after processing the first connection material (4).
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: March 31, 2020
    Assignee: DANFOSS SILICON POWER GMBH
    Inventors: Frank Osterwald, Martin Becker, Holger Ulrich, Ronald Eisele, Jacek Rudzki
  • Patent number: 10593608
    Abstract: A semiconductor module (10) contains a ceramic interconnect device (50) having at least one semiconductor component (20). The at least one semiconductor component (20) is covered by an encapsulating compound (30) which contains a cured inorganic cement and has a thermal expansion coefficient in the range of 2 to 10 ppm/K. The ceramic of the ceramic interconnect device (50) is selected from ceramics based on aluminum oxide, aluminum nitride or silicon nitride.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: March 17, 2020
    Assignee: Heraeus Deutschland GmbH & Co. KG
    Inventors: Ronald Eisele, Anton-Zoran Miric, Frank Krüger, Wolfgang Schmitt
  • Patent number: 10483229
    Abstract: Sintering device for sintering at least one electronic assembly, having a lower die and an upper die which is slidable towards the lower die, or a lower die which is slidable towards the upper die. The lower die forms a support for the assembly to be sintered and the upper die includes a receptacle for a pressure pad for exerting pressure directed towards the lower die, and a delimitation wall which laterally surrounds the pressure pad. The delimitation wall having an outer delimitation wall and an inner delimitation wall surrounded by the outer delimitation wall, the inner delimitation wall mounted so as to be slidable towards the outer delimitation wall and so as to be slid in the direction of the lower die such that, following the placing of the inner delimitation wall on the lower die, the pressure pad is displaceable in the direction of the lower die.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: November 19, 2019
    Assignee: Danfoss Silicon Power GmbH
    Inventors: Frank Osterwald, Ronald Eisele, Martin Becker, Lars Paulsen, Jacek Rudzki, Holger Ulrich