Abstract: A FET IC structure made using a back-side access process that mitigates or eliminates thermal conductivity problems. In some embodiments, electrically-isolated thermal paths are formed adjacent the FET and configured to conduct heat laterally away from the FET to generally orthogonal thermal pathways, and thence to thermal pads externally accessible at the “top” of the completed IC. In some embodiments having a thermally-conductive handle wafer, electrically-isolated thermal paths are formed adjacent a FET and configured to conduct heat laterally away from the FET. Thermal vias are formed sufficiently so as to be in thermal contact with the handle wafer and with the conventional metallization layers of the device superstructure, at least one of which is in thermal contact with the lateral thermal paths. In some embodiments, the lateral thermal paths may use dummy gates configured to conduct heat laterally away from a FET to generally orthogonal thermal pathways.

Abstract: Methods and apparatuses for use in tuning reactance are described. Open loop and closed loop control for tuning of reactances are also described. Tunable inductors and/or tunable capacitors may be used in filters, resonant circuits, matching networks, and phase shifters. Ability to control inductance and/or capacitance in a circuit leads to flexibility in operation of the circuit, since the circuit may be tuned to operate under a range of different operating frequencies.

Abstract: Methods and apparatuses for use in tuning reactance are described. Open loop and closed loop control for tuning of reactances are also described. Tunable inductors and/or tunable capacitors may be used in filters, resonant circuits, matching networks, and phase shifters. Ability to control inductance and/or capacitance in a circuit leads to flexibility in operation of the circuit, since the circuit may be tuned to operate under a range of different operating frequencies.

Abstract: A FET IC structure made using a back-side access process that mitigates or eliminates thermal conductivity problems. In some embodiments, electrically-isolated thermal paths are formed adjacent the FET and configured to conduct heat laterally away from the FET to generally orthogonal thermal pathways, and thence to thermal pads externally accessible at the “top” of the completed IC. In some embodiments having a thermally-conductive handle wafer, electrically-isolated thermal paths are formed adjacent a FET and configured to conduct heat laterally away from the FET. Thermal vias are formed sufficiently so as to be in thermal contact with the handle wafer and with the conventional metallization layers of the device superstructure, at least one of which is in thermal contact with the lateral thermal paths. In some embodiments, the lateral thermal paths may use dummy gates configured to conduct heat laterally away from a FET to generally orthogonal thermal pathways.

Abstract: An apparatus for detecting difference in operating characteristics of a main circuit by using a replica circuit is presented. In one exemplary case, a sensed difference in operating characteristics of the two circuits is used to drive a tuning control loop to minimize the sensed difference. In another exemplary case, several replica circuits of the main circuit are used, where each is isolated from one or more operating variables that affect the operating characteristic of the main circuit. Each replica circuit can be used for sensing a different operating characteristic, or, two replica circuits can be combined to sense a same operating characteristic.

Abstract: A FET IC structure made using a back-side access process that mitigates or eliminates thermal conductivity problems. In some embodiments, electrically-isolated thermal paths are formed adjacent the FET and configured to conduct heat laterally away from the FET to generally orthogonal thermal pathways, and thence to thermal pads externally accessible at the “top” of the completed IC. In some embodiments having a thermally-conductive handle wafer, electrically-isolated thermal paths are formed adjacent a FET and configured to conduct heat laterally away from the FET. Thermal vias are formed sufficiently so as to be in thermal contact with the handle wafer and with the conventional metallization layers of the device superstructure, at least one of which is in thermal contact with the lateral thermal paths. In some embodiments, the lateral thermal paths may use dummy gates configured to conduct heat laterally away from a FET to generally orthogonal thermal pathways.

Abstract: Structures and fabrication methods for transistors having low parasitic capacitance, the transistors including an insulating low dielectric constant first or second handle wafer. In one embodiment, a Single Layer Transfer technique is used to position an insulating LDC handle wafer proximate the metal interconnect layers of an SOI transistor/metal layer stack in lieu of the silicon substrate of conventional designs. In another embodiment, a Double Layer Transfer technique is used to replace the silicon substrate of prior art structures with an insulating LDC substrate. In some embodiments, the insulating LDC handle wafer includes at least one air cavity, which reduces the effective dielectric constant of material surrounding an RF FET. An insulating LDC handle wafer reduces insertion loss and non-linearity, increases isolation, provides for more ideal voltage division of stacked transistors, enables a higher Q factor due to lower coupling losses, and otherwise mitigates various parasitic effects.

Abstract: A single supply RF switch driver. The single supply RF switch driver includes an inverter, where a first resistor has been integrated within the inverter, and the resistor is connected to an RF switch. In one aspect, the integration of the first resistor within the inverter allows for the elimination of a negative power supply for the inverter, while maximizing the isolation achieved in the RF switch. In another aspect, the driver is a configured to have a second resistor integrated within the inverter. A third resistor is connected between the gate of the RF switch and the inverter. In an alternate aspect, the driver operates from a positive power supply and a negative power supply, thus increasing the isolation in the RF switch even further.

Abstract: Novel integrated circuits (SOI ICs), and methods for making and mounting the ICs are disclosed. In one embodiment, an IC comprises a first circuit layer of the IC formed from an active layer of an SOI wafer. The first circuit layer is coupled to a first surface of buffer layer, and a second surface of the buffer layer is coupled to a selected substrate comprising an insulating material. The selected substrate may be selected, without limitation, from the following types: sapphire, quartz, silicon dioxide glass, piezoelectric materials, and ceramics. A second circuit layer of the IC are formed, coupled to a second surface of the selected substrate. In one embodiment of a mounted IC, the first circuit layer is coupled to contact pads on a package substrate via solder bumps or copper pillars. The second circuit layer is coupled to contact pads on the package substrate via wire bonds.

Abstract: An extension of conventional IC fabrication processes to include some of the concepts of flip-chip assemblies while producing a final “non-flip chip” circuit structure suitable for conventional packaging or for direct usage by customers. Multiple IC dies are fabricated on a semiconductor wafer in a conventional fashion, solder bumped or the like, and singulated. The singulated dies, which may be of different sizes and functionality, are then flip-chip assembled onto a single tile substrate of thin-film material which has been patterned with vias, peripheral connection pads, and one or more ground planes. Once dies are flip-chip mounted to the thin-film tile, all of the dies on the entire tile may be probed using automated testing equipment. Sets of dies of different functionality may be tested as a system or subsystem. Once test probing is complete, the dies (or sets of dies) and tile are singulated into die/tile assemblies.

Abstract: A FET IC structure made using a back-side access process that mitigates or eliminates thermal conductivity problems. In some embodiments, electrically-isolated thermal paths are formed adjacent the FET and configured to conduct heat laterally away from the FET to generally orthogonal thermal pathways, and thence to thermal pads externally accessible at the “top” of the completed IC. In some embodiments having a thermally-conductive handle wafer, electrically-isolated thermal paths are formed adjacent a FET and configured to conduct heat laterally away from the FET. Thermal vias are formed sufficiently so as to be in thermal contact with the handle wafer and with the conventional metallization layers of the device superstructure, at least one of which is in thermal contact with the lateral thermal paths. In some embodiments, the lateral thermal paths may use dummy gates configured to conduct heat laterally away from a FET to generally orthogonal thermal pathways.

Abstract: A die seal is broken in at least one place for a conductor strip formed on each conductor layer. Accordingly, no current can flow in a circular pattern around the entire perimeter of the chip. In some embodiments, an angled slot is provided in the original die seal. The angled slots may be vertically aligned. Alternatively, the slots may be vertically staggered or straight. When vertically staggered, the slots on each conductor layer are vertically offset.

Abstract: Methods and apparatuses for use in tuning reactance are described. Open loop and closed loop control for tuning of reactances are also described. Tunable inductors and/or tunable capacitors may be used in filters, resonant circuits, matching networks, and phase shifters. Ability to control inductance and/or capacitance in a circuit leads to flexibility in operation of the circuit, since the circuit may be tuned to operate under a range of different operating frequencies.

Abstract: A single supply RF switch driver. The single supply RF switch driver includes an inverter, where a first resistor has been integrated within the inverter, and the resistor is connected to an RF switch. In one aspect, the integration of the first resistor within the inverter allows for the elimination of a negative power supply for the inverter, while maximizing the isolation achieved in the RF switch. In another aspect, the driver is a configured to have a second resistor integrated within the inverter. A third resistor is connected between the gate of the RF switch and the inverter. In an alternate aspect, the driver operates from a positive power supply and a negative power supply, thus increasing the isolation in the RF switch even further.

Abstract: An apparatus for detecting difference in operating characteristics of a main circuit by using a replica circuit is presented. In one exemplary case, a sensed difference in operating characteristics of the two circuits is used to drive a tuning control loop to minimize the sensed difference. In another exemplary case, several replica circuits of the main circuit are used, where each is isolated from one or more operating variables that affect the operating characteristic of the main circuit. Each replica circuit can be used for sensing a different operating characteristic, or, two replica circuits can be combined to sense a same operating characteristic.

Abstract: An extension of conventional IC fabrication processes to include some of the concepts of flip-chip assemblies while producing a final “non-flip chip” circuit structure suitable for conventional packaging or for direct usage by customers. Multiple IC dies are fabricated on a semiconductor wafer in a conventional fashion, solder bumped or the like, and singulated. The singulated dies, which may be of different sizes and functionality, are then flip-chip assembled onto a single tile substrate of thin-film material which has been patterned with vias, peripheral connection pads, and one or more ground planes. Once dies are flip-chip mounted to the thin-film tile, all of the dies on the entire tile may be probed using automated testing equipment. Sets of dies of different functionality may be tested as a system or subsystem. Once test probing is complete, the dies (or sets of dies) and tile are singulated into die/tile assemblies.

Abstract: Structures and fabrication methods for transistors having low parasitic capacitance, the transistors including an insulating low dielectric constant first or second handle wafer. In one embodiment, a Single Layer Transfer technique is used to position an insulating LDC handle wafer proximate the metal interconnect layers of an SOI transistor/metal layer stack in lieu of the silicon substrate of conventional designs. In another embodiment, a Double Layer Transfer technique is used to replace the silicon substrate of prior art structures with an insulating LDC substrate. In some embodiments, the insulating LDC handle wafer includes at least one air cavity, which reduces the effective dielectric constant of material surrounding an RF FET. An insulating LDC handle wafer reduces insertion loss and non-linearity, increases isolation, provides for more ideal voltage division of stacked transistors, enables a higher Q factor due to lower coupling losses, and otherwise mitigates various parasitic effects.

Abstract: An apparatus for detecting difference in operating characteristics of a main circuit by using a replica circuit is presented. In one exemplary case, a sensed difference in operating characteristics of the two circuits is used to drive a tuning control loop to minimize the sensed difference. In another exemplary case, several replica circuits of the main circuit are used, where each is isolated from one or more operating variables that affect the operating characteristic of the main circuit. Each replica circuit can be used for sensing a different operating characteristic, or, two replica circuits can be combined to sense a same operating characteristic.

Abstract: A die seal is broken in at least one place for a conductor strip formed on each conductor layer. Accordingly, no current can flow in a circular pattern around the entire perimeter of the chip. In some embodiments, an angled slot is provided in the original die seal. The angled slots may be vertically aligned. Alternatively, the slots may be vertically staggered or straight. When vertically staggered, the slots on each conductor layer are vertically offset.

Abstract: An extension of conventional IC fabrication processes to include some of the concepts of flip-chip assemblies while producing a final “non-flip chip” circuit structure suitable for conventional packaging or for direct usage by customers. Multiple IC dies are fabricated on a semiconductor wafer in a conventional fashion, solder bumped or the like, and singulated. The singulated dies, which may be of different sizes and functionality, are then flip-chip assembled onto a single tile substrate of thin-film material which has been patterned with vias, peripheral connection pads, and one or more ground planes. Once dies are flip-chip mounted to the thin-film tile, all of the dies on the entire tile may be probed using automated testing equipment. Sets of dies of different functionality may be tested as a system or subsystem. Once test probing is complete, the dies (or sets of dies) and tile are singulated into die/tile assemblies.