Abstract: One embodiment of the present invention provides a system that facilitates high-bandwidth communication using a flexible bridge. This system includes a chip with an active face upon which active circuitry and signal pads reside, and a second component with a surface upon which active circuitry and/or signal pads reside. A flexible bridge provides high-bandwidth communication between the active face of the chip and the surface of the second component. By matching the wire line size in the flexible bridge to the size of circuits and/or signal pads on the chip and on the second component, the system allows signals to be sent between the circuits on the chip and the second component without having to change the scale of the interconnect, thereby alleviating wireability and bandwidth limitations of conventional chip packaging technologies.

Abstract: One embodiment of the present invention provides a system that facilitates high-bandwidth communication using a flexible bridge. This system includes a chip with an active face upon which active circuitry and signal pads reside, and a second component with a surface upon which active circuitry and/or signal pads reside. A flexible bridge provides high-bandwidth communication between the active face of the chip and the surface of the second component. This flexible bridge provides a flexible connection that allows the chip to be moved with six degrees of freedom relative to the second component without affecting communication between the chip and the second component. Hence, the flexible bridge allows the chip and the second component to communicate without requiring precise alignment between the chip and the second component.

Abstract: One embodiment of the present invention provides a system that measures alignment between a first semiconductor die and a second semiconductor die. The system operates by applying a pattern of voltage signals to a two-dimensional array of conductive transmitter elements that form a transmitter array on the first semiconductor die. This transmitter array is positioned over a corresponding two-dimensional array of conductive receiver elements that form a receiver array on the second semiconductor die, whereby a voltage signal applied to a transmitter element induces a voltage signal in one or more receiver elements. The system amplifies voltage signals induced in receiver elements in the receiver array, and subsequently analyzes the amplified signals to determine an alignment between the first semiconductor die and the second semiconductor die.

Abstract: One embodiment of the present invention provides an arrangement of differential pairs of wires that carry differential signals across a semiconductor chip. In this arrangement, differential pairs of wires are organized within a set of parallel tracks on the semiconductor chip. Furthermore, differential pairs of wires are organized to be non-adjacent within the tracks. This means that each true wire is separated from its corresponding complement wire by at least one intervening wire in the set of parallel tracks, thereby reducing coupling capacitance between corresponding true and complement wires. Moreover, this arrangement may include one or more twisting structures, wherein a twisting structure twists a differential pair of wires so that the corresponding true and complement wires are interchanged within the set of parallel tracks.

Abstract: An electrical circuit for determining a capacitance is described. The electrical circuit includes a first device, a rectifying circuit and a feedback circuit. The first device has a first terminal and a second terminal. The first device has a first unknown capacitance and the first terminal may be configured to receive a time-varying voltage signal. The rectifying circuit has an input terminal, an output terminal and a feedback terminal. The input terminal may be coupled to the second terminal and the output terminal may be configured for coupling to an output electrical circuit. The feedback circuit may selectively couple the output terminal to the input terminal using the feedback terminal such that the output terminal and the input terminal are substantially at a common voltage.

Abstract: One embodiment of the present invention provides a system that performs voltage sampling over an extended voltage range on a semiconductor chip. During operation, the system receives an input voltage at a node within the semiconductor chip. The system samples the input voltage through a first sampling pathway using NMOS pass gates, which latch the input voltage to produce a first output signal. This first output signal tracks the input voltage from ground up to a cut-off voltage for the nMOS pass gates. The system also samples the input voltage through a second sampling pathway using nMOS pass gates, which latch the input voltage to produce a second output signal. Prior to the NMOS pass gates along the second sampling pathway, the input voltage passes through a source-follower gate, which translates the input voltage down, so that the second output signal tracks the input voltage from a turn-on voltage of the source-follower gate up to Vdd.

Abstract: A system that improves communications between capacitively coupled integrated circuit chips. The system operates by situating an interposer over capacitive communication pads on a first integrated circuit chip, wherein the interposer is made up of material that is anisotropic with respect to transmitting capacitive signals. A second integrated circuit chip is situated so that communication pads on the second integrated circuit chip are aligned to capacitively couple signals between the integrated circuit chips through the interposer. The increased dielectric permittivity caused by the interposer can improve capacitive coupling between opposing communication pads on the integrated circuit chips. The interposer can also reduce cross talk between communication pads on the first integrated circuit chip and pads adjacent to the opposing communication pads on the second integrated circuit chip.

Abstract: One embodiment of the present invention provides a system that writes to a cell in a memory using a low-voltage-swing signal across a pair of global bit-lines. During operation, the system receives a low-voltage-swing signal across a pair of global bit-lines, which is too low to reliably write the memory cell. Next, the system converts the low-voltage-swing signal to a high-voltage-swing signal, which is adequate to reliably write the memory cell. The system then writes to the memory cell by applying the high-voltage-swing signal across a pair of local bit-lines that are coupled to the memory cell. The use of low-voltage-swing signals on the global bit-lines reduces overall power consumption. Furthermore, in one embodiment of the present invention, the voltage conversion is achieved using a pair of cross-coupled NMOS transistors whose sources are directly or indirectly coupled with the global bit-lines, and whose drains are directly or indirectly coupled with the local bit-lines.

Abstract: One embodiment of the present invention provides a technique for assembling semiconductor chips. First, multiple semiconductor chips are permanently laminated together into a plurality of laminated chip assemblies, wherein the semiconductor chips within the laminated chip assembly communicate with each other through electrically conductive connections. Next, laminated chip assemblies are stacked together to form a stack of semiconductor chips without permanently bonding the laminated chip assemblies together, wherein the laminated chip assemblies communicate with each other using capacitive coupling.

Abstract: One embodiment of the present invention provides an electronic circuit and method for measuring a capacitance. A signal generating mechanism generates a signal having a predefined frequency and predefined low and high voltage levels on one terminal of the capacitance. The other terminal of the capacitance is coupled to a switching mechanism. The switching mechanism is set to couple the other terminal of the capacitance to a first amplifier or a second amplifier for a portion of each signal cycle thereby full-wave rectifying a transient current flowing between the two terminals in the capacitance. Outputs of the first amplifier and the second amplifier are coupled to a current measurement mechanism for measuring the current. The capacitance is determined from the measured current. Several variations on this embodiment are provided.

Abstract: One embodiment of the present invention provides a system that facilitates proximity communication using a bridge chip. This system includes a base chip with an active face, upon which active circuitry and signal pads reside, and a back face opposite the active face. The bridge chip is mounted to the base chip using a mounting, interconnection, and communication structure. The bridge chip is positioned so that a free end is proximate to a neighboring chip, thereby supporting proximity communication between the base chip and the neighboring chip.

Abstract: One embodiment of the present invention provides a system that improves communications between capacitively coupled integrated circuit chips. The system operates by situating an interposer over capacitive communication pads on a first integrated circuit chip, wherein the interposer is made up of material that is anisotropic with respect to transmitting capacitive signals. A second integrated circuit chip is situated so that communication pads on the second integrated circuit chip are aligned to capacitively couple signals between the integrated circuit chips through the interposer. The increased dielectric permittivity caused by the interposer can improve capacitive coupling between opposing communication pads on the integrated circuit chips. The interposer can also reduce cross talk between communication pads on the first integrated circuit chip and pads adjacent to the opposing communication pads on the second integrated circuit chip.

Abstract: One embodiment of the present invention provides a system that operatively couples an integrated circuit with a microstrip transmission line through chip lamination. The system includes a first semiconductor die containing the integrated circuit, and a second semiconductor die containing the microstrip transmission line. Unlike metal lines in the integrated circuit, which have relatively small cross-sections, the microstrip transmission line has a cross-section that is large enough so that signal propagation is governed by inductance and capacitance (LC) instead of resistance and capacitance (RC). The first semiconductor die and the second semiconductor die are laminated together so that the integrated circuit on the first semiconductor die is operatively coupled with the microstrip transmission line in the second semiconductor die.

Abstract: One embodiment of the present invention provides a capacitively-coupled receiver amplifier that has an input with no DC coupling. A DC voltage is programmed on the input. During programming, a transmitter is held at a voltage at a midpoint between a voltage that represents a logical “1” and a voltage that represents a logical “0” and the input voltage of the receiver amplifier is programmed to be substantially the switching-threshold voltage for the receiver amplifier. Then, during normal data communication, the transmitter drives high and low electrical signals that are coupled to the receiver amplifier. Since the input of the receiver amplifier has been substantially set to the DC voltage, the receiver amplifier need not control the DC voltage of the input for each transition in the electrical signals.

Abstract: One embodiment of the present invention provides a system which drives on-chip wires using capacitive coupling. During operation, the system drives a signal onto a driven wire. This signal feeds from the driven wire through a coupling capacitor onto a coupled wire, which is an on-chip wire that routes the signal to its destination. Feeding the signal through the coupling capacitor reduces the voltage swing of the corresponding coupled signal on the coupled wire, thereby lessening the power required to drive the coupled signal on the coupled wire.

Abstract: One embodiment of the present invention provides a technique for assembling semiconductor chips. First, multiple semiconductor chips are permanently laminated together into a plurality of laminated chip assemblies, wherein the semiconductor chips within the laminated chip assembly communicate with each other through electrically conductive connections. Next, laminated chip assemblies are stacked together to form a stack of semiconductor chips without permanently bonding the laminated chip assemblies together, wherein the laminated chip assemblies communicate with each other using capacitive coupling.

Abstract: One embodiment of the present invention provides an electronic circuit and method for measuring a capacitance. A signal generating mechanism generates a signal having a predefined frequency and predefined low and high voltage levels on one terminal of the capacitance. The other terminal of the capacitance is coupled to a switching mechanism. The switching mechanism is set to couple the other terminal of the capacitance to a first amplifier or a second amplifier for a portion of each signal cycle thereby full-wave rectifying a transient current flowing between the two terminals in the capacitance. Outputs of the first amplifier and the second amplifier are coupled to a current measurement mechanism for measuring the current. The capacitance is determined from the measured current. Several variations on this embodiment are provided.

Abstract: One embodiment of the present invention provides a capacitively-coupled receiver amplifier that has an input with no DC coupling. A DC voltage is programmed on the input. During programming, a transmitter is held at a voltage at a midpoint between a voltage that represents a logical “1” and a voltage that represents a logical “0” and the input voltage of the receiver amplifier is programmed to be substantially the switching-threshold voltage for the receiver amplifier. Then, during normal data communication, the transmitter drives high and low electrical signals that are coupled to the receiver amplifier. Since the input of the receiver amplifier has been substantially set to the DC voltage, the receiver amplifier need not control the DC voltage of the input for each transition in the electrical signals.

Abstract: One embodiment of the present invention provides an arrangement of differential pairs of wires that carry differential signals across a semiconductor chip. In this arrangement, differential pairs of wires are organized within a set of parallel tracks on the semiconductor chip. Furthermore, differential pairs of wires are organized to be non-adjacent within the tracks. This means that each true wire is separated from its corresponding complement wire by at least one intervening wire in the set of parallel tracks, thereby reducing coupling capacitance between corresponding true and complement wires. Moreover, this arrangement may include one or more twisting structures, wherein a twisting structure twists a differential pair of wires so that the corresponding true and complement wires are interchanged within the set of parallel tracks.

Abstract: One embodiment of the present invention provides a system that asynchronously controls the sending of data items from a sender to a receiver. The system includes a data path between the sender and the receiver, a first control path between the sender and the receiver, and a second control path between the sender and the receiver. The first control path and the second control path alternately control the asynchronous transmission of consecutive data items on the data path between the sender and the receiver.