Abstract: A memory circuit arrangement and fabrication method thereof are presented in which the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the other (logic circuit) substrate. The control circuit controls sequences when reading, writing or erasing content of a memory cell. The logic circuit substrate also contains a CPU and encryption coprocessor. The memory circuit contains a sense amplifier, with the aid of which the memory state of a memory cell can be determined, and a decoding circuit that selects a word or bit line.

Abstract: This document discusses, among other things, apparatus having at least one CMOS transistor overlying a substrate; and at least one finned bipolar transistor overlying the substrate and methods for making the apparatus.

Abstract: A method for producing a tunnel field-effect transistor is disclosed. Connection regions of different doping types are produced by means of self-aligning implantation methods.

Abstract: In a memory circuit arrangement and fabrication method, the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the other (logic circuit) substrate. The control circuit controls sequences when reading, writing or erasing content of a memory cell. The logic circuit substrate also contains a CPU and encryption coprocessor. The memory circuit contains a sense amplifier, with the aid of which the memory state of a memory cell can be determined, and a decoding circuit that selects a word or bit line.

Abstract: A memory cell includes a FinFET select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element.

Abstract: A device utilizing a breakdown layer in combination with a programmable resistance material, a phase-change material or a threshold switching material. The breakdown layer having damage.

Abstract: In a memory circuit arrangement and fabrication method, the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the other (logic circuit) substrate. The control circuit controls sequences when reading, writing or erasing content of a memory cell. The logic circuit substrate also contains a CPU and encryption coprocessor. The memory circuit contains a sense amplifier, with the aid of which the memory state of a memory cell can be determined, and a decoding circuit that selects a word or bit line.

Abstract: An intergrated circuit having a drive circuit is disclosed. One embodiment provides an intergrated memory circuit arrangement with a drive circuit for an EEPROM. In one embodiment, the drive circuit contains tunnel field effect transistors and can be produced in particular on a small chip area.

Abstract: The invention relates to a bit line structure having a surface bit line (DLx) and a buried bit line (SLx), the buried bit line (SLx) being formed in a trench with a trench insulation layer (6) and being connected to doping regions (10) with which contact is to be made via a covering connecting layer (12) and a self-aligning terminal layer (13) in an upper partial region of the trench.

Abstract: The disclosure relates to a bit line structure and an associated production method for the bit line structure. In the bit line structure, at least in a region of a second contact and a plurality of first contact adjoining the latter, an isolation trench is filled with an electrically conductive trench filling layer. The isolation trench connects to the first doping regions adjoining the second contact for the purpose of realizing a buried contact bypass line.

Abstract: A memory cell includes a memory element and a nanotube transistor contacting the memory element for accessing the memory element.

Abstract: The invention relates to a method for producing a PCM memory element and to a corresponding PCM element.

Abstract: An integrated circuit has a high voltage area, a logic area and a memory array for forming a system on a chip that includes linear, logic and memory devices. The memory array has floating gate transistors disposed in a triple well structure with a raised drain bit line 13 substantially vertically aligned with a buried source bit line 14. The memory array separates the columns with deep trenches 46 that may also be formed into charge pump capacitors.

Abstract: The invention relates to a bit line structure having a surface bit line (DLx) and a buried bit line (SLx), the buried bit line (SLx) being formed in a trench with a trench insulation layer (6) and being connected to doping regions (10) with which contact is to be made via a covering connecting layer (12) and a self-aligning terminal layer (13) in an upper partial region of the trench.

Abstract: The invention relates to a bit line structure having a surface bit line (DLx) and a buried bit line (SLx), the buried bit line (SLx) being formed in a trench with a trench insulation layer (6) and being connected to doping regions (10) with which contact is to be made via a covering connecting layer (12) and a self-aligning terminal layer (13) in an upper partial region of the trench.

Abstract: Deep trench isolation structures and methods of formation thereof are disclosed. Several methods of and structures for increasing the threshold voltage of a parasitic transistor formed proximate deep trench isolation structures are described, including implanting a channel stop region into the bottom surface of the deep trench isolation structures, partially filling a bottom portion of the deep trench isolation structures with an insulating material, and/or filling at least a portion of the deep trench isolation structures with a doped polysilicon material.

Abstract: A vertical field-effect transistor having a semiconductor layer, in which a doped channel region is arranged along a depression. A “buried” terminal region leads as far as a surface of the semiconductor layer. The field-effect transistor also has a doped terminal region near an opening of the depression as well as the doped terminal region remote from the opening, a control region arranged in the depression, and an electrical insulating region between the control region and the channel region. The terminal region remote from the opening leads as far as a surface containing the opening or is electrically conductively connected to an electrically conductive connection leading to the surface. The control region is arranged in only one depression. The field-effect transistor is a drive transistor at a word line or at a bit line of a memory cell array.

Abstract: The disclosure relates to a bit line structure and an associated production method for the bit line structure. In the bit line structure, at least in a region of a second contact and a plurality of first contact adjoining the latter, an isolation trench is filled with an electrically conductive trench filling layer. The isolation trench connects to the first doping regions adjoining the second contact for the purpose of realizing a buried contact bypass line.

Abstract: A memory circuit arrangement and a fabrication method are disclosed. The memory circuit arrangement has a memory cell area. The memory cell area contains memory cell transistors, one column of which are selected using a triple gate area selection transistor. The transistor has gate area that extends into isolating trenches. The isolating trenches isolate the memory cell in different columns of the memory cell array.

Abstract: A bit line structure and associated fabrication method are provided for a semiconductor element or circuit arrangement. The bit line structure contains a surface bit line and a buried bit line. The buried bit line is formed in an upper section of a trench and is connected to an associated first doping region via a first connection layer. A first trench filling layer, which is insulated from the buried bit line by a second trench insulating layer, is situated in a lower section of the trench.